Re: [PATCH 6/9] phy: cadence: sierra: Don't configure if any plls are already locked

2020-11-09 Thread Philipp Zabel
On Tue, 2020-11-03 at 09:25 +0530, Kishon Vijay Abraham I wrote: > From: Faiz Abbas > > Serdes lanes might be shared between multiple cores in some usecases > and its not possible to lock PLLs for both the lanes independently > by the two cores. This requires a bootloader to configure both the >

[PATCH 6/9] phy: cadence: sierra: Don't configure if any plls are already locked

2020-11-02 Thread Kishon Vijay Abraham I
From: Faiz Abbas Serdes lanes might be shared between multiple cores in some usecases and its not possible to lock PLLs for both the lanes independently by the two cores. This requires a bootloader to configure both the lanes at early boot time. To handle this case, skip all configuration if