On Fri, Jun 27, 2014 at 12:22:17PM +0100, Sudeep Holla wrote:
> Hi Mark,
>
> Thanks for the review.
>
> On 27/06/14 11:36, Mark Rutland wrote:
> > Hi Sudeep,
> >
> > On Wed, Jun 25, 2014 at 06:30:42PM +0100, Sudeep Holla wrote:
> >> From: Sudeep Holla
> >>
> >> This patch adds support for
Hi Mark,
Thanks for the review.
On 27/06/14 11:36, Mark Rutland wrote:
Hi Sudeep,
On Wed, Jun 25, 2014 at 06:30:42PM +0100, Sudeep Holla wrote:
From: Sudeep Holla
This patch adds support for cacheinfo on ARM64.
On ARMv8, the cache hierarchy can be identified through Cache Level ID
(CLIDR)
Hi Sudeep,
On Wed, Jun 25, 2014 at 06:30:42PM +0100, Sudeep Holla wrote:
> From: Sudeep Holla
>
> This patch adds support for cacheinfo on ARM64.
>
> On ARMv8, the cache hierarchy can be identified through Cache Level ID
> (CLIDR) register while the cache geometry is provided by Cache Size ID
Hi Sudeep,
On Wed, Jun 25, 2014 at 06:30:42PM +0100, Sudeep Holla wrote:
From: Sudeep Holla sudeep.ho...@arm.com
This patch adds support for cacheinfo on ARM64.
On ARMv8, the cache hierarchy can be identified through Cache Level ID
(CLIDR) register while the cache geometry is provided by
Hi Mark,
Thanks for the review.
On 27/06/14 11:36, Mark Rutland wrote:
Hi Sudeep,
On Wed, Jun 25, 2014 at 06:30:42PM +0100, Sudeep Holla wrote:
From: Sudeep Holla sudeep.ho...@arm.com
This patch adds support for cacheinfo on ARM64.
On ARMv8, the cache hierarchy can be identified through
On Fri, Jun 27, 2014 at 12:22:17PM +0100, Sudeep Holla wrote:
Hi Mark,
Thanks for the review.
On 27/06/14 11:36, Mark Rutland wrote:
Hi Sudeep,
On Wed, Jun 25, 2014 at 06:30:42PM +0100, Sudeep Holla wrote:
From: Sudeep Holla sudeep.ho...@arm.com
This patch adds support for
From: Sudeep Holla
This patch adds support for cacheinfo on ARM64.
On ARMv8, the cache hierarchy can be identified through Cache Level ID
(CLIDR) register while the cache geometry is provided by Cache Size ID
(CCSIDR) register.
Since the architecture doesn't provide any way of detecting the
From: Sudeep Holla sudeep.ho...@arm.com
This patch adds support for cacheinfo on ARM64.
On ARMv8, the cache hierarchy can be identified through Cache Level ID
(CLIDR) register while the cache geometry is provided by Cache Size ID
(CCSIDR) register.
Since the architecture doesn't provide any way
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