Re: [PATCH 8/9] platform/x86: intel_pmc_core: Add LTR registers for Tiger Lake

2021-04-07 Thread Rajneesh Bhardwaj
Please ignore the typo in my previous email and use this tag instead. Acked-by: Rajneesh Bhardwaj On Wed, Apr 7, 2021 at 11:48 AM Rajneesh Bhardwaj wrote: > > Acked-by: Rajneesh Bhardwaj > > On Wed, Mar 31, 2021 at 11:06 PM David E. Box > wrote: > > > > From: Gayatri Kammela > > > > Just

Re: [PATCH 8/9] platform/x86: intel_pmc_core: Add LTR registers for Tiger Lake

2021-04-07 Thread Rajneesh Bhardwaj
Acked-by: Rajneesh Bhardwaj On Wed, Mar 31, 2021 at 11:06 PM David E. Box wrote: > > From: Gayatri Kammela > > Just like Ice Lake, Tiger Lake uses Cannon Lake's LTR information > and supports a few additional registers. Hence add the LTR registers > specific to Tiger Lake to the

Re: [PATCH 8/9] platform/x86: intel_pmc_core: Add LTR registers for Tiger Lake

2021-04-07 Thread Hans de Goede
Hi, On 4/1/21 5:05 AM, David E. Box wrote: > From: Gayatri Kammela > > Just like Ice Lake, Tiger Lake uses Cannon Lake's LTR information > and supports a few additional registers. Hence add the LTR registers > specific to Tiger Lake to the cnp_ltr_show_map[]. > > Also adjust the number of LTR

[PATCH 8/9] platform/x86: intel_pmc_core: Add LTR registers for Tiger Lake

2021-03-31 Thread David E. Box
From: Gayatri Kammela Just like Ice Lake, Tiger Lake uses Cannon Lake's LTR information and supports a few additional registers. Hence add the LTR registers specific to Tiger Lake to the cnp_ltr_show_map[]. Also adjust the number of LTR IPs for Tiger Lake to the correct amount. Signed-off-by: