On 2019-09-21 03:50, Stephen Boyd wrote:
Quoting Lina Iyer (2019-09-17 14:50:20)
On Fri, Sep 13 2019 at 13:53 -0600, Lina Iyer wrote:
>On Thu, Sep 05 2019 at 18:03 -0600, Stephen Boyd wrote:
>>Quoting Lina Iyer (2019-09-03 10:07:22)
>>>On Mon, Sep 02 2019 at 07:58 -0600, Marc Zyngier wrote:
Quoting Lina Iyer (2019-09-17 14:50:20)
> On Fri, Sep 13 2019 at 13:53 -0600, Lina Iyer wrote:
> >On Thu, Sep 05 2019 at 18:03 -0600, Stephen Boyd wrote:
> >>Quoting Lina Iyer (2019-09-03 10:07:22)
> >>>On Mon, Sep 02 2019 at 07:58 -0600, Marc Zyngier wrote:
> On 02/09/2019 14:38, Rob Herring w
Adding Sibi
On Fri, Sep 13 2019 at 13:53 -0600, Lina Iyer wrote:
Sorry, I couldn't get to this earlier.
On Thu, Sep 05 2019 at 18:03 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2019-09-03 10:07:22)
On Mon, Sep 02 2019 at 07:58 -0600, Marc Zyngier wrote:
On 02/09/2019 14:38, Rob Herring wro
Sorry, I couldn't get to this earlier.
On Thu, Sep 05 2019 at 18:03 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2019-09-03 10:07:22)
On Mon, Sep 02 2019 at 07:58 -0600, Marc Zyngier wrote:
>On 02/09/2019 14:38, Rob Herring wrote:
>> On Thu, Aug 29, 2019 at 12:11:54PM -0600, Lina Iyer wrote:
T
On Wed, Sep 11 2019 at 04:05 -0600, Linus Walleij wrote:
On Thu, Aug 29, 2019 at 8:47 PM Lina Iyer wrote:
+- qcom,scm-spi-cfg:
+ Usage: optional
+ Value type:
+ Definition: Specifies if the SPI configuration registers have to be
+ written from the firmware.
On Thu, Aug 29, 2019 at 8:47 PM Lina Iyer wrote:
> +- qcom,scm-spi-cfg:
> + Usage: optional
> + Value type:
> + Definition: Specifies if the SPI configuration registers have to be
> + written from the firmware.
> +
> Example:
>
> pdc: interrupt-contro
Quoting Lina Iyer (2019-09-03 10:07:22)
> On Mon, Sep 02 2019 at 07:58 -0600, Marc Zyngier wrote:
> >On 02/09/2019 14:38, Rob Herring wrote:
> >> On Thu, Aug 29, 2019 at 12:11:54PM -0600, Lina Iyer wrote:
> >>> In addition to configuring the PDC, additional registers that interface
> >>> the GIC ha
On Mon, Sep 02 2019 at 07:58 -0600, Marc Zyngier wrote:
On 02/09/2019 14:38, Rob Herring wrote:
On Thu, Aug 29, 2019 at 12:11:54PM -0600, Lina Iyer wrote:
In addition to configuring the PDC, additional registers that interface
the GIC have to be configured to match the GPIO type. The registers
On 02/09/2019 14:38, Rob Herring wrote:
> On Thu, Aug 29, 2019 at 12:11:54PM -0600, Lina Iyer wrote:
>> In addition to configuring the PDC, additional registers that interface
>> the GIC have to be configured to match the GPIO type. The registers on
>> some QCOM SoCs are access restricted, while on
On Thu, Aug 29, 2019 at 12:11:54PM -0600, Lina Iyer wrote:
> In addition to configuring the PDC, additional registers that interface
> the GIC have to be configured to match the GPIO type. The registers on
> some QCOM SoCs are access restricted, while on other SoCs are not. They
> SoCs with access
In addition to configuring the PDC, additional registers that interface
the GIC have to be configured to match the GPIO type. The registers on
some QCOM SoCs are access restricted, while on other SoCs are not. They
SoCs with access restriction to these SPI registers need to be written
from the firm
11 matches
Mail list logo
