David, Thanks for the comments. I am working on addressing your feedback.
Comments inline below.
On 7/29/2017 4:36 PM, David Miller wrote:
From: Babu Moger
Date: Thu, 27 Jul 2017 15:57:29 -0600
@@ -600,7 +600,7 @@ niagara_tlb_fixup:
be,pt %xcc,
David, Thanks for the comments. I am working on addressing your feedback.
Comments inline below.
On 7/29/2017 4:36 PM, David Miller wrote:
From: Babu Moger
Date: Thu, 27 Jul 2017 15:57:29 -0600
@@ -600,7 +600,7 @@ niagara_tlb_fixup:
be,pt %xcc, niagara4_patch
nop
From: Babu Moger
Date: Thu, 27 Jul 2017 15:57:29 -0600
> @@ -600,7 +600,7 @@ niagara_tlb_fixup:
> be,pt %xcc, niagara4_patch
>nop
> cmp %g1, SUN4V_CHIP_SPARC_M7
> - be,pt %xcc, niagara4_patch
> + be,pt %xcc, sparc_m7_patch
>nop
From: Babu Moger
Date: Thu, 27 Jul 2017 15:57:29 -0600
> @@ -600,7 +600,7 @@ niagara_tlb_fixup:
> be,pt %xcc, niagara4_patch
>nop
> cmp %g1, SUN4V_CHIP_SPARC_M7
> - be,pt %xcc, niagara4_patch
> + be,pt %xcc, sparc_m7_patch
>nop
> cmp %g1,
New algorithm that takes advantage of the M7 block init store
ASI, ie, overlapping pipelines and miss buffer filling.
Full details in code comments.
Signed-off-by: Babu Moger
---
arch/sparc/kernel/head_64.S | 12 +-
arch/sparc/lib/M7copy_from_user.S | 41 ++
New algorithm that takes advantage of the M7 block init store
ASI, ie, overlapping pipelines and miss buffer filling.
Full details in code comments.
Signed-off-by: Babu Moger
---
arch/sparc/kernel/head_64.S | 12 +-
arch/sparc/lib/M7copy_from_user.S | 41 ++
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