Re: [PATCH RFC v4 06/13] perf vendor events arm64: Add hip09 SMMUv3 PMCG events

2020-10-15 Thread John Garry
On 14/10/2020 19:06, Robin Murphy wrote: +    "EventCode": "0x8a", +    "EventName": "smmuv3_pmcg.L1_TLB", +    "BriefDescription": "SMMUv3 PMCG L1 TABLE transation", +    "PublicDescription": "SMMUv3 PMCG L1 TABLE transation", Those typos are either missing "c"s or "l"s, but w

Re: [PATCH RFC v4 06/13] perf vendor events arm64: Add hip09 SMMUv3 PMCG events

2020-10-14 Thread Robin Murphy
On 2020-10-08 11:15, John Garry wrote: Add the SMMUv3 PMCG (Performance Monitor Event Group) events for hip09 platform. This contains a mix of architected and IMP def events Signed-off-by: John Garry --- .../hisilicon/hip09/sys/smmu-v3-pmcg.json | 42 +++ 1 file changed,

[PATCH RFC v4 06/13] perf vendor events arm64: Add hip09 SMMUv3 PMCG events

2020-10-08 Thread John Garry
Add the SMMUv3 PMCG (Performance Monitor Event Group) events for hip09 platform. This contains a mix of architected and IMP def events Signed-off-by: John Garry --- .../hisilicon/hip09/sys/smmu-v3-pmcg.json | 42 +++ 1 file changed, 42 insertions(+) create mode 100644 tool