On 3/11/2021 6:07 AM, Peter Zijlstra wrote:
On Wed, Mar 10, 2021 at 08:37:44AM -0800, kan.li...@linux.intel.com wrote:
From: Kan Liang
The hardware cache events are different among hybrid PMUs. Each hybrid
PMU should have its own hw cache event table.
Reviewed-by: Andi Kleen
Signed-off-by
On Wed, Mar 10, 2021 at 08:37:44AM -0800, kan.li...@linux.intel.com wrote:
> From: Kan Liang
>
> The hardware cache events are different among hybrid PMUs. Each hybrid
> PMU should have its own hw cache event table.
>
> Reviewed-by: Andi Kleen
> Signed-off-by: Kan Liang
> ---
> arch/x86/event
From: Kan Liang
The hardware cache events are different among hybrid PMUs. Each hybrid
PMU should have its own hw cache event table.
Reviewed-by: Andi Kleen
Signed-off-by: Kan Liang
---
arch/x86/events/core.c | 11 +--
arch/x86/events/perf_event.h | 9 +
2 files changed
3 matches
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