RE: [PATCH V2 2/2] ata: ahci: ceva: Update the driver to support xilinx GT phy

2020-09-22 Thread Piyush Mehta
; Srinivas Goud ; Michal Simek Subject: Re: [PATCH V2 2/2] ata: ahci: ceva: Update the driver to support xilinx GT phy On Tue, 2020-09-22 at 15:45 +0530, Piyush Mehta wrote: > SATA controller used in Xilinx ZynqMP platform uses xilinx GT phy > which has 4 GT lanes and can used by 4 perip

Re: [PATCH V2 2/2] ata: ahci: ceva: Update the driver to support xilinx GT phy

2020-09-22 Thread Philipp Zabel
On Tue, 2020-09-22 at 15:45 +0530, Piyush Mehta wrote: > SATA controller used in Xilinx ZynqMP platform uses xilinx GT phy > which has 4 GT lanes and can used by 4 peripherals at a time. > SATA controller uses 1 GT phy lane among the 4 GT lanes. To configure > the GT lane for SATA controller, the

[PATCH V2 2/2] ata: ahci: ceva: Update the driver to support xilinx GT phy

2020-09-22 Thread Piyush Mehta
SATA controller used in Xilinx ZynqMP platform uses xilinx GT phy which has 4 GT lanes and can used by 4 peripherals at a time. SATA controller uses 1 GT phy lane among the 4 GT lanes. To configure the GT lane for SATA controller, the below sequence is expected. 1. Assert the SATA controller