On Tue, May 30, 2017 at 05:16:27PM -0700, Florian Fainelli wrote:
> On 05/30/2017 05:06 PM, Andrew Lunn wrote:
> >> - past the initial setup, if we start creating bridge devices and so on,
> >> we have no way to tell: group Ports 0-3 together and send traffic to CPU
> >> port 0, then let Port 5
On Tue, May 30, 2017 at 05:16:27PM -0700, Florian Fainelli wrote:
> On 05/30/2017 05:06 PM, Andrew Lunn wrote:
> >> - past the initial setup, if we start creating bridge devices and so on,
> >> we have no way to tell: group Ports 0-3 together and send traffic to CPU
> >> port 0, then let Port 5
On 05/30/2017 05:06 PM, Andrew Lunn wrote:
>> - past the initial setup, if we start creating bridge devices and so on,
>> we have no way to tell: group Ports 0-3 together and send traffic to CPU
>> port 0, then let Port 5 alone and send traffic to CPU port 1, that's a
>> DSA-only problem though,
On 05/30/2017 05:06 PM, Andrew Lunn wrote:
>> - past the initial setup, if we start creating bridge devices and so on,
>> we have no way to tell: group Ports 0-3 together and send traffic to CPU
>> port 0, then let Port 5 alone and send traffic to CPU port 1, that's a
>> DSA-only problem though,
> - past the initial setup, if we start creating bridge devices and so on,
> we have no way to tell: group Ports 0-3 together and send traffic to CPU
> port 0, then let Port 5 alone and send traffic to CPU port 1, that's a
> DSA-only problem though, because we still have the CPU port(s) as
>
> - past the initial setup, if we start creating bridge devices and so on,
> we have no way to tell: group Ports 0-3 together and send traffic to CPU
> port 0, then let Port 5 alone and send traffic to CPU port 1, that's a
> DSA-only problem though, because we still have the CPU port(s) as
>
+Jiri, Ido,
On 05/30/2017 03:44 AM, John Crispin wrote:
> Some boards have two CPU interfaces connected to the switch, e.g. WiFi
> access points, with 1 port labeled WAN, 4 ports labeled lan1-lan4, and
> two port connected to the SoC.
>
> This patch extends DSA to allows both CPU ports to be
+Jiri, Ido,
On 05/30/2017 03:44 AM, John Crispin wrote:
> Some boards have two CPU interfaces connected to the switch, e.g. WiFi
> access points, with 1 port labeled WAN, 4 ports labeled lan1-lan4, and
> two port connected to the SoC.
>
> This patch extends DSA to allows both CPU ports to be
Hi John,
Vivien Didelot writes:
>> +int port_cpu = ds->ports[port].upstream;
>
> ds->ports[port] is p->dp.
I misread this part, p is not yet allocated in that chunk, please ignore
this one comment ;-)
Thanks,
Vivien
Hi John,
Vivien Didelot writes:
>> +int port_cpu = ds->ports[port].upstream;
>
> ds->ports[port] is p->dp.
I misread this part, p is not yet allocated in that chunk, please ignore
this one comment ;-)
Thanks,
Vivien
Hi John,
John Crispin writes:
> +static inline bool dsa_is_upstream_port(struct dsa_switch *ds, int p)
> +{
> + return dsa_is_cpu_port(ds, p) || dsa_is_dsa_port(ds, p);
> +}
This looks confusing to me. What DSA calls an "upstream" port for the
moment is the port which
Hi John,
John Crispin writes:
> +static inline bool dsa_is_upstream_port(struct dsa_switch *ds, int p)
> +{
> + return dsa_is_cpu_port(ds, p) || dsa_is_dsa_port(ds, p);
> +}
This looks confusing to me. What DSA calls an "upstream" port for the
moment is the port which goes to the CPU
On 05/30/2017 12:15 PM, Florian Fainelli wrote:
> Hi John,
>
> On 05/30/2017 11:37 AM, John Crispin wrote:
>> Hi,
>>
>> the patch series is based on net-next from 12 hours ago and works fine
>> on that tree. I compile and runtime tested it quite intensively on
>> various boards
>
> The warning
On 05/30/2017 12:15 PM, Florian Fainelli wrote:
> Hi John,
>
> On 05/30/2017 11:37 AM, John Crispin wrote:
>> Hi,
>>
>> the patch series is based on net-next from 12 hours ago and works fine
>> on that tree. I compile and runtime tested it quite intensively on
>> various boards
>
> The warning
Hi John,
On 05/30/2017 11:37 AM, John Crispin wrote:
> Hi,
>
> the patch series is based on net-next from 12 hours ago and works fine
> on that tree. I compile and runtime tested it quite intensively on
> various boards
The warning is legit though:
572if (dsa_port_is_cpu(port))
Hi John,
On 05/30/2017 11:37 AM, John Crispin wrote:
> Hi,
>
> the patch series is based on net-next from 12 hours ago and works fine
> on that tree. I compile and runtime tested it quite intensively on
> various boards
The warning is legit though:
572if (dsa_port_is_cpu(port))
Hi,
the patch series is based on net-next from 12 hours ago and works fine
on that tree. I compile and runtime tested it quite intensively on
various boards
John
On 30/05/17 17:38, kbuild test robot wrote:
Hi John,
[auto build test ERROR on net-next/master]
[also build test ERROR on
Hi,
the patch series is based on net-next from 12 hours ago and works fine
on that tree. I compile and runtime tested it quite intensively on
various boards
John
On 30/05/17 17:38, kbuild test robot wrote:
Hi John,
[auto build test ERROR on net-next/master]
[also build test ERROR on
Hi John,
[auto build test ERROR on net-next/master]
[also build test ERROR on next-20170530]
[cannot apply to v4.12-rc3]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
Hi John,
[auto build test ERROR on net-next/master]
[also build test ERROR on next-20170530]
[cannot apply to v4.12-rc3]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
Some boards have two CPU interfaces connected to the switch, e.g. WiFi
access points, with 1 port labeled WAN, 4 ports labeled lan1-lan4, and
two port connected to the SoC.
This patch extends DSA to allows both CPU ports to be used. The "cpu"
node in the DSA tree can now have a phandle to the
Some boards have two CPU interfaces connected to the switch, e.g. WiFi
access points, with 1 port labeled WAN, 4 ports labeled lan1-lan4, and
two port connected to the SoC.
This patch extends DSA to allows both CPU ports to be used. The "cpu"
node in the DSA tree can now have a phandle to the
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