On 9 October 2018 07:01:57 BST, Veerabhadrarao Badiganti
wrote:
>Hi
>
>
>On 10/8/2018 12:26 PM, Bjorn Andersson wrote:
>> On Sun 07 Oct 01:07 PDT 2018, Craig wrote:
>>
>>> Any updates on this?
>>>
>> FWIW I used qcom,sdhci-msm-v5 on QCS404 successfully.
>>
>> Regards,
>> Bjorn
>
>The base
On 9 October 2018 07:01:57 BST, Veerabhadrarao Badiganti
wrote:
>Hi
>
>
>On 10/8/2018 12:26 PM, Bjorn Andersson wrote:
>> On Sun 07 Oct 01:07 PDT 2018, Craig wrote:
>>
>>> Any updates on this?
>>>
>> FWIW I used qcom,sdhci-msm-v5 on QCS404 successfully.
>>
>> Regards,
>> Bjorn
>
>The base
Hi
On 10/8/2018 12:26 PM, Bjorn Andersson wrote:
On Sun 07 Oct 01:07 PDT 2018, Craig wrote:
Any updates on this?
FWIW I used qcom,sdhci-msm-v5 on QCS404 successfully.
Regards,
Bjorn
The base address and interrupt numbers needs to be updated in your dt.
you can refer the below link to
Hi
On 10/8/2018 12:26 PM, Bjorn Andersson wrote:
On Sun 07 Oct 01:07 PDT 2018, Craig wrote:
Any updates on this?
FWIW I used qcom,sdhci-msm-v5 on QCS404 successfully.
Regards,
Bjorn
The base address and interrupt numbers needs to be updated in your dt.
you can refer the below link to
On Sun 07 Oct 01:07 PDT 2018, Craig wrote:
> Any updates on this?
>
FWIW I used qcom,sdhci-msm-v5 on QCS404 successfully.
Regards,
Bjorn
> On 25 September 2018 16:39:33 BST, Craig wrote:
> >
> >
> >On 25 September 2018 12:17:26 BST, Veerabhadrarao Badiganti
> > wrote:
> >>
> >>On 9/25/2018
On Sun 07 Oct 01:07 PDT 2018, Craig wrote:
> Any updates on this?
>
FWIW I used qcom,sdhci-msm-v5 on QCS404 successfully.
Regards,
Bjorn
> On 25 September 2018 16:39:33 BST, Craig wrote:
> >
> >
> >On 25 September 2018 12:17:26 BST, Veerabhadrarao Badiganti
> > wrote:
> >>
> >>On 9/25/2018
Any updates on this?
On 25 September 2018 16:39:33 BST, Craig wrote:
>
>
>On 25 September 2018 12:17:26 BST, Veerabhadrarao Badiganti
> wrote:
>>
>>On 9/25/2018 1:18 AM, Craig Tatlor wrote:
>>> What socs have you tested this on?
>>> On sdm660 it seems to crash device
>>> when writing pwr ctl.
>>
Any updates on this?
On 25 September 2018 16:39:33 BST, Craig wrote:
>
>
>On 25 September 2018 12:17:26 BST, Veerabhadrarao Badiganti
> wrote:
>>
>>On 9/25/2018 1:18 AM, Craig Tatlor wrote:
>>> What socs have you tested this on?
>>> On sdm660 it seems to crash device
>>> when writing pwr ctl.
>>
On 25 September 2018 12:17:26 BST, Veerabhadrarao Badiganti
wrote:
>
>On 9/25/2018 1:18 AM, Craig Tatlor wrote:
>> What socs have you tested this on?
>> On sdm660 it seems to crash device
>> when writing pwr ctl.
>
>Hi
>We have tested this on SDM845.
>SDM660 also has SDCC5 controller, so you
On 25 September 2018 12:17:26 BST, Veerabhadrarao Badiganti
wrote:
>
>On 9/25/2018 1:18 AM, Craig Tatlor wrote:
>> What socs have you tested this on?
>> On sdm660 it seems to crash device
>> when writing pwr ctl.
>
>Hi
>We have tested this on SDM845.
>SDM660 also has SDCC5 controller, so you
On 9/25/2018 1:18 AM, Craig Tatlor wrote:
What socs have you tested this on?
On sdm660 it seems to crash device
when writing pwr ctl.
Hi
We have tested this on SDM845.
SDM660 also has SDCC5 controller, so you would need to define
"qcom,sdhci-msm-v5" in your platform dt.
Can you confirm if
On 9/25/2018 1:18 AM, Craig Tatlor wrote:
What socs have you tested this on?
On sdm660 it seems to crash device
when writing pwr ctl.
Hi
We have tested this on SDM845.
SDM660 also has SDCC5 controller, so you would need to define
"qcom,sdhci-msm-v5" in your platform dt.
Can you confirm if
What socs have you tested this on?
On sdm660 it seems to crash device
when writing pwr ctl.
On Tue, Jun 19, 2018 at 11:09:17AM +0530, Vijay Viswanath wrote:
> With SDCC5, the MCI register space got removed and the offset/order of
> several registers have changed. Based on SDCC version used and
What socs have you tested this on?
On sdm660 it seems to crash device
when writing pwr ctl.
On Tue, Jun 19, 2018 at 11:09:17AM +0530, Vijay Viswanath wrote:
> With SDCC5, the MCI register space got removed and the offset/order of
> several registers have changed. Based on SDCC version used and
On 19 June 2018 at 07:39, Vijay Viswanath wrote:
> With SDCC5, the MCI register space got removed and the offset/order of
> several registers have changed. Based on SDCC version used and the register,
> we need to pick the base address and offset.
>
> Depends on patch series: "[PATCH V5 0/2] mmc:
On 19 June 2018 at 07:39, Vijay Viswanath wrote:
> With SDCC5, the MCI register space got removed and the offset/order of
> several registers have changed. Based on SDCC version used and the register,
> we need to pick the base address and offset.
>
> Depends on patch series: "[PATCH V5 0/2] mmc:
With SDCC5, the MCI register space got removed and the offset/order of
several registers have changed. Based on SDCC version used and the register,
we need to pick the base address and offset.
Depends on patch series: "[PATCH V5 0/2] mmc: sdhci-msm: Configuring IO_PAD
support for sdhci-msm"
With SDCC5, the MCI register space got removed and the offset/order of
several registers have changed. Based on SDCC version used and the register,
we need to pick the base address and offset.
Depends on patch series: "[PATCH V5 0/2] mmc: sdhci-msm: Configuring IO_PAD
support for sdhci-msm"
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