Re: [PATCH V4 5/6] iommu/arm-smmu: Add support for MMU40x/500 clocks

2017-07-10 Thread Vivek Gautam
Hi Rob, On 07/10/2017 09:07 AM, Rob Herring wrote: On Thu, Jul 06, 2017 at 03:07:04PM +0530, Vivek Gautam wrote: From: Sricharan R The MMU400x/500 is the implementation of the SMMUv2 arch specification. It is split in to two blocks TBU, TCU. TBU caches the page

Re: [PATCH V4 5/6] iommu/arm-smmu: Add support for MMU40x/500 clocks

2017-07-10 Thread Vivek Gautam
Hi Rob, On 07/10/2017 09:07 AM, Rob Herring wrote: On Thu, Jul 06, 2017 at 03:07:04PM +0530, Vivek Gautam wrote: From: Sricharan R The MMU400x/500 is the implementation of the SMMUv2 arch specification. It is split in to two blocks TBU, TCU. TBU caches the page table, instantiated for each

Re: [PATCH V4 5/6] iommu/arm-smmu: Add support for MMU40x/500 clocks

2017-07-09 Thread Rob Herring
On Thu, Jul 06, 2017 at 03:07:04PM +0530, Vivek Gautam wrote: > From: Sricharan R > > The MMU400x/500 is the implementation of the SMMUv2 > arch specification. It is split in to two blocks > TBU, TCU. TBU caches the page table, instantiated > for each master locally,

Re: [PATCH V4 5/6] iommu/arm-smmu: Add support for MMU40x/500 clocks

2017-07-09 Thread Rob Herring
On Thu, Jul 06, 2017 at 03:07:04PM +0530, Vivek Gautam wrote: > From: Sricharan R > > The MMU400x/500 is the implementation of the SMMUv2 > arch specification. It is split in to two blocks > TBU, TCU. TBU caches the page table, instantiated > for each master locally, clocked by the TBUn_clk. >

[PATCH V4 5/6] iommu/arm-smmu: Add support for MMU40x/500 clocks

2017-07-06 Thread Vivek Gautam
From: Sricharan R The MMU400x/500 is the implementation of the SMMUv2 arch specification. It is split in to two blocks TBU, TCU. TBU caches the page table, instantiated for each master locally, clocked by the TBUn_clk. TCU manages the address translation with PTW and

[PATCH V4 5/6] iommu/arm-smmu: Add support for MMU40x/500 clocks

2017-07-06 Thread Vivek Gautam
From: Sricharan R The MMU400x/500 is the implementation of the SMMUv2 arch specification. It is split in to two blocks TBU, TCU. TBU caches the page table, instantiated for each master locally, clocked by the TBUn_clk. TCU manages the address translation with PTW and has the programming