Hi Morimoto-san
Thanks for your comments,
I will address your findings in next version
Thanks,
Jiada
On 2018/12/04 10:52, Kuninori Morimoto wrote:
Hi Jiada
There are AVB Counter Clocks in ADG, each clock has 12bits integral
and 8 bits fractional dividers which operates with S0D1ϕ clock.
Hi Morimoto-san
Thanks for your comments,
I will address your findings in next version
Thanks,
Jiada
On 2018/12/04 10:52, Kuninori Morimoto wrote:
Hi Jiada
There are AVB Counter Clocks in ADG, each clock has 12bits integral
and 8 bits fractional dividers which operates with S0D1ϕ clock.
Hi Vladimir
Thanks for your comments
I will address your findings in next version
Thanks,
Jiada
On 2018/12/03 21:53, Vladimir Zapolskiy wrote:
Hi Jiada,
On 12/03/2018 01:24 PM, jiada_w...@mentor.com wrote:
From: Jiada Wang
There are AVB Counter Clocks in ADG, each clock has 12bits
Hi Vladimir
Thanks for your comments
I will address your findings in next version
Thanks,
Jiada
On 2018/12/03 21:53, Vladimir Zapolskiy wrote:
Hi Jiada,
On 12/03/2018 01:24 PM, jiada_w...@mentor.com wrote:
From: Jiada Wang
There are AVB Counter Clocks in ADG, each clock has 12bits
HI Jiada
> There are AVB Counter Clocks in ADG, each clock has 12bits integral
> and 8 bits fractional dividers which operates with S0D1ϕ clock.
>
> This patch registers 8 AVB Counter Clocks when clock-cells of
> rcar_sound node is 2,
>
> Signed-off-by: Jiada Wang
> ---
>
HI Jiada
> There are AVB Counter Clocks in ADG, each clock has 12bits integral
> and 8 bits fractional dividers which operates with S0D1ϕ clock.
>
> This patch registers 8 AVB Counter Clocks when clock-cells of
> rcar_sound node is 2,
>
> Signed-off-by: Jiada Wang
> ---
>
Hi Jiada
> There are AVB Counter Clocks in ADG, each clock has 12bits integral
> and 8 bits fractional dividers which operates with S0D1ϕ clock.
>
> This patch registers 8 AVB Counter Clocks when clock-cells of
> rcar_sound node is 2,
>
> Signed-off-by: Jiada Wang
> ---
(snip)
> +struct
Hi Jiada
> There are AVB Counter Clocks in ADG, each clock has 12bits integral
> and 8 bits fractional dividers which operates with S0D1ϕ clock.
>
> This patch registers 8 AVB Counter Clocks when clock-cells of
> rcar_sound node is 2,
>
> Signed-off-by: Jiada Wang
> ---
(snip)
> +struct
Hi Jiada,
On 12/03/2018 01:24 PM, jiada_w...@mentor.com wrote:
> From: Jiada Wang
>
> There are AVB Counter Clocks in ADG, each clock has 12bits integral
> and 8 bits fractional dividers which operates with S0D1ϕ clock.
>
> This patch registers 8 AVB Counter Clocks when clock-cells of
>
Hi Jiada,
On 12/03/2018 01:24 PM, jiada_w...@mentor.com wrote:
> From: Jiada Wang
>
> There are AVB Counter Clocks in ADG, each clock has 12bits integral
> and 8 bits fractional dividers which operates with S0D1ϕ clock.
>
> This patch registers 8 AVB Counter Clocks when clock-cells of
>
From: Jiada Wang
There are AVB Counter Clocks in ADG, each clock has 12bits integral
and 8 bits fractional dividers which operates with S0D1ϕ clock.
This patch registers 8 AVB Counter Clocks when clock-cells of
rcar_sound node is 2,
Signed-off-by: Jiada Wang
---
sound/soc/sh/rcar/adg.c |
From: Jiada Wang
There are AVB Counter Clocks in ADG, each clock has 12bits integral
and 8 bits fractional dividers which operates with S0D1ϕ clock.
This patch registers 8 AVB Counter Clocks when clock-cells of
rcar_sound node is 2,
Signed-off-by: Jiada Wang
---
sound/soc/sh/rcar/adg.c |
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