Registers of Marvell chips are organized in internal SMI devices.
One of them at address 0x1C is called Global2. It provides an extended
set of registers, used for interrupt control, EEPROM access, indirect
PHY access (to bypass the PHY Polling Unit) and cross-chip setup.
Most chips have it, but
Registers of Marvell chips are organized in internal SMI devices.
One of them at address 0x1C is called Global2. It provides an extended
set of registers, used for interrupt control, EEPROM access, indirect
PHY access (to bypass the PHY Polling Unit) and cross-chip setup.
Most chips have it, but
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