[PATCH net-next 0/9] net: dsa: mv88e6xxx: STP and Global 2 cleanup

The Marvell switches registers are organized in distinct internal SMI devices, such as PHY, Port, Global 1 or Global 2 registers sets. Since not all chips support every registers sets or have slightly differences in them (such as old 88E6060 or new 88E6390 likely to be supported soon), make the

[PATCH net-next 0/9] net: dsa: mv88e6xxx: STP and Global 2 cleanup

The Marvell switches registers are organized in distinct internal SMI devices, such as PHY, Port, Global 1 or Global 2 registers sets. Since not all chips support every registers sets or have slightly differences in them (such as old 88E6060 or new 88E6390 likely to be supported soon), make the