On Thu, Jun 26, 2014 at 11:08 AM, Stephen Warren wrote:
> On 06/25/2014 05:30 PM, Andrew Bresticker wrote:
>> On Wed, Jun 25, 2014 at 3:12 PM, Stephen Warren
>> wrote:
>>> On 06/18/2014 12:16 AM, Andrew Bresticker wrote:
In addition to the PCIe and SATA PHYs, the XUSB pad controller also
On 06/27/2014 09:00 AM, Felipe Balbi wrote:
> On Wed, Jun 25, 2014 at 04:30:48PM -0700, Andrew Bresticker wrote:
+static int usb3_phy_power_on(struct phy *phy)
+{
+ struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
+ int port = usb3_phy_to_port(phy);
+
On Wed, Jun 25, 2014 at 04:30:48PM -0700, Andrew Bresticker wrote:
> >> +static int usb3_phy_power_on(struct phy *phy)
> >> +{
> >> + struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
> >> + int port = usb3_phy_to_port(phy);
> >> + int lane = padctl->usb3_ports[port].lane;
> >>
On Wed, Jun 25, 2014 at 04:30:48PM -0700, Andrew Bresticker wrote:
+static int usb3_phy_power_on(struct phy *phy)
+{
+ struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
+ int port = usb3_phy_to_port(phy);
+ int lane = padctl-usb3_ports[port].lane;
+ u32 value,
On 06/27/2014 09:00 AM, Felipe Balbi wrote:
On Wed, Jun 25, 2014 at 04:30:48PM -0700, Andrew Bresticker wrote:
+static int usb3_phy_power_on(struct phy *phy)
+{
+ struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
+ int port = usb3_phy_to_port(phy);
+ int lane =
On Thu, Jun 26, 2014 at 11:08 AM, Stephen Warren swar...@wwwdotorg.org wrote:
On 06/25/2014 05:30 PM, Andrew Bresticker wrote:
On Wed, Jun 25, 2014 at 3:12 PM, Stephen Warren swar...@wwwdotorg.org
wrote:
On 06/18/2014 12:16 AM, Andrew Bresticker wrote:
In addition to the PCIe and SATA PHYs,
On 06/25/2014 05:30 PM, Andrew Bresticker wrote:
> On Wed, Jun 25, 2014 at 3:12 PM, Stephen Warren wrote:
>> On 06/18/2014 12:16 AM, Andrew Bresticker wrote:
>>> In addition to the PCIe and SATA PHYs, the XUSB pad controller also
>>> supports 3 UTMI, 2 HSIC, and 2 USB3 PHYs. Each USB3 PHY uses a
On 06/25/2014 05:30 PM, Andrew Bresticker wrote:
On Wed, Jun 25, 2014 at 3:12 PM, Stephen Warren swar...@wwwdotorg.org wrote:
On 06/18/2014 12:16 AM, Andrew Bresticker wrote:
In addition to the PCIe and SATA PHYs, the XUSB pad controller also
supports 3 UTMI, 2 HSIC, and 2 USB3 PHYs. Each
On Wed, Jun 25, 2014 at 3:12 PM, Stephen Warren wrote:
> On 06/18/2014 12:16 AM, Andrew Bresticker wrote:
>> In addition to the PCIe and SATA PHYs, the XUSB pad controller also
>> supports 3 UTMI, 2 HSIC, and 2 USB3 PHYs. Each USB3 PHY uses a single
>> PCIe or SATA lane and is mapped to one of
On 06/18/2014 12:16 AM, Andrew Bresticker wrote:
> In addition to the PCIe and SATA PHYs, the XUSB pad controller also
> supports 3 UTMI, 2 HSIC, and 2 USB3 PHYs. Each USB3 PHY uses a single
> PCIe or SATA lane and is mapped to one of the three UTMI ports.
>
> diff --git
On 06/18/2014 12:16 AM, Andrew Bresticker wrote:
In addition to the PCIe and SATA PHYs, the XUSB pad controller also
supports 3 UTMI, 2 HSIC, and 2 USB3 PHYs. Each USB3 PHY uses a single
PCIe or SATA lane and is mapped to one of the three UTMI ports.
diff --git
On Wed, Jun 25, 2014 at 3:12 PM, Stephen Warren swar...@wwwdotorg.org wrote:
On 06/18/2014 12:16 AM, Andrew Bresticker wrote:
In addition to the PCIe and SATA PHYs, the XUSB pad controller also
supports 3 UTMI, 2 HSIC, and 2 USB3 PHYs. Each USB3 PHY uses a single
PCIe or SATA lane and is
In addition to the PCIe and SATA PHYs, the XUSB pad controller also
supports 3 UTMI, 2 HSIC, and 2 USB3 PHYs. Each USB3 PHY uses a single
PCIe or SATA lane and is mapped to one of the three UTMI ports.
Signed-off-by: Andrew Bresticker
---
drivers/pinctrl/pinctrl-tegra-xusb.c | 1106
In addition to the PCIe and SATA PHYs, the XUSB pad controller also
supports 3 UTMI, 2 HSIC, and 2 USB3 PHYs. Each USB3 PHY uses a single
PCIe or SATA lane and is mapped to one of the three UTMI ports.
Signed-off-by: Andrew Bresticker abres...@chromium.org
---
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