On 9/29/20 7:29 PM, Pratyush Yadav wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> On 29/09/20 03:42PM, tudor.amba...@microchip.com wrote:
>> Hi, Pratyush,
>>
>> I'm replying to v10 so that we continue the discussion, but this applies to
On 9/29/20 9:12 PM, tudor.amba...@microchip.com wrote:
> Hi, Pratyush,
>
> I'm replying to v10 so that we continue the discussion, but this applies to
> v13 as well.
>
> On 7/21/20 2:29 PM, Pratyush Yadav wrote:
>
@@ -2368,12 +2517,16 @@ spi_nor_spimem_adjust_hwcaps(struct spi_nor
On 29/09/20 03:42PM, tudor.amba...@microchip.com wrote:
> Hi, Pratyush,
>
> I'm replying to v10 so that we continue the discussion, but this applies to
> v13 as well.
>
> On 7/21/20 2:29 PM, Pratyush Yadav wrote:
>
> >>> @@ -2368,12 +2517,16 @@ spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor,
Hi, Pratyush,
I'm replying to v10 so that we continue the discussion, but this applies to v13
as well.
On 7/21/20 2:29 PM, Pratyush Yadav wrote:
>>> @@ -2368,12 +2517,16 @@ spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor,
>>> u32 *hwcaps)
>>> struct spi_nor_flash_parameter *params =
Hi Tudor,
On 07/07/20 05:37PM, tudor.amba...@microchip.com wrote:
> Hi, Pratyush,
>
> On 6/23/20 9:30 PM, Pratyush Yadav wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> > content is safe
> >
> > Double Transfer Rate (DTR) is SPI protocol in which data is
Hi, Pratyush,
On 6/23/20 9:30 PM, Pratyush Yadav wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> Double Transfer Rate (DTR) is SPI protocol in which data is transferred
> on each clock edge as opposed to on each clock cycle. Make
>
Double Transfer Rate (DTR) is SPI protocol in which data is transferred
on each clock edge as opposed to on each clock cycle. Make
framework-level changes to allow supporting flashes in DTR mode.
Right now, mixed DTR modes are not supported. So, for example a mode
like 4S-4D-4D will not work. All
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