Re: [PATCH v13 08/15] mtd: spi-nor: core: do 2 byte reads for SR and FSR in DTR mode

2020-09-30 Thread Pratyush Yadav
On 30/09/20 06:50AM, tudor.amba...@microchip.com wrote: > On 9/16/20 3:44 PM, Pratyush Yadav wrote: > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the > > content is safe > > > > Some controllers, like the cadence qspi controller, have trouble reading > > only 1 byte

Re: [PATCH v13 08/15] mtd: spi-nor: core: do 2 byte reads for SR and FSR in DTR mode

2020-09-30 Thread Tudor.Ambarus
On 9/16/20 3:44 PM, Pratyush Yadav wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the > content is safe > > Some controllers, like the cadence qspi controller, have trouble reading > only 1 byte in DTR mode. So, do 2 byte reads for SR and FSR commands in did you

[PATCH v13 08/15] mtd: spi-nor: core: do 2 byte reads for SR and FSR in DTR mode

2020-09-16 Thread Pratyush Yadav