On Mon, 5 Oct 2020 21:01:23 +0530, Pratyush Yadav wrote:
> This series adds support for Octal DTR flashes in the SPI NOR framework,
> and then adds hooks for the Cypress Semper and Micron Xcella flashes to
> allow running them in Octal DTR mode. This series assumes that the flash
> is handed to
Hi Tudor,
On 28/10/20 07:53AM, tudor.amba...@microchip.com wrote:
> Hi, Pratyush,
>
> On 10/5/20 6:31 PM, Pratyush Yadav wrote:
> > Tested on Micron MT35X and S28HS flashes for Octal DTR.
>
> Do these flashes define the "Command Sequences to Change to
> Octal DDR (8D-8D-8D) mode" table? Can't
On 10/28/20 8:51 PM, tudor.amba...@microchip.com wrote:
> On 10/28/20 2:49 PM, Pratyush Yadav wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
>> content is safe
>>
>> Hi Tudor,
>>
>> On 28/10/20 07:53AM, tudor.amba...@microchip.com wrote:
>>> Hi, Pratyush,
Hi, Pratyush,
On 10/5/20 6:31 PM, Pratyush Yadav wrote:
> Tested on Micron MT35X and S28HS flashes for Octal DTR.
Do these flashes define the "Command Sequences to Change to
Octal DDR (8D-8D-8D) mode" table? Can't we use that table
instead of defining our own octal dtr enable functions?
I see
On 28/10/20 03:21PM, tudor.amba...@microchip.com wrote:
> On 10/28/20 2:49 PM, Pratyush Yadav wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> > content is safe
> >
> > Hi Tudor,
> >
> > On 28/10/20 07:53AM, tudor.amba...@microchip.com wrote:
> >> Hi,
On 10/28/20 2:49 PM, Pratyush Yadav wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> Hi Tudor,
>
> On 28/10/20 07:53AM, tudor.amba...@microchip.com wrote:
>> Hi, Pratyush,
>>
>> On 10/5/20 6:31 PM, Pratyush Yadav wrote:
>>> Tested on
Hi,
This series adds support for Octal DTR flashes in the SPI NOR framework,
and then adds hooks for the Cypress Semper and Micron Xcella flashes to
allow running them in Octal DTR mode. This series assumes that the flash
is handed to the kernel in Legacy SPI mode.
Tested on Micron MT35X and
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