On Tue, Aug 16, 2016 at 08:40:08PM +, Zhengyu Shen wrote:
> > > > > + hrtimer_start(_mmdc->hrtimer, mmdc_timer_period(),
> > > > > + HRTIMER_MODE_REL_PINNED);
> > > >
> > > > Why is a hrtimer necessary? Is this just copy-pasted from CCN, or do
> > > > you have similar
On Tue, Aug 16, 2016 at 08:40:08PM +, Zhengyu Shen wrote:
> > > > > + hrtimer_start(_mmdc->hrtimer, mmdc_timer_period(),
> > > > > + HRTIMER_MODE_REL_PINNED);
> > > >
> > > > Why is a hrtimer necessary? Is this just copy-pasted from CCN, or do
> > > > you have similar
> > > > + hrtimer_start(_mmdc->hrtimer, mmdc_timer_period(),
> > > > + HRTIMER_MODE_REL_PINNED);
> > >
> > > Why is a hrtimer necessary? Is this just copy-pasted from CCN, or do
> > > you have similar HW issues?
> > >
> > > Is there no overflow interrupt?
> >
> > When
> > > > + hrtimer_start(_mmdc->hrtimer, mmdc_timer_period(),
> > > > + HRTIMER_MODE_REL_PINNED);
> > >
> > > Why is a hrtimer necessary? Is this just copy-pasted from CCN, or do
> > > you have similar HW issues?
> > >
> > > Is there no overflow interrupt?
> >
> > When
> > Added cpumask and migration handling support to driver
> > Validated event during event_init
> > Added code to properly stop counters
> > Used perf_invalid_context instead of perf_sw_context
> > Added hrtimer to poll for overflow
> > Added better description
> >
> > Added cpumask and migration handling support to driver
> > Validated event during event_init
> > Added code to properly stop counters
> > Used perf_invalid_context instead of perf_sw_context
> > Added hrtimer to poll for overflow
> > Added better description
> >
On Tue, Aug 16, 2016 at 02:40:43PM +, Zhengyu Shen wrote:
> > > Added cpumask and migration handling support to driver
> > > Validated event during event_init
> > > Added code to properly stop counters
> > > Used perf_invalid_context instead of perf_sw_context
> > > Added hrtimer to
On Tue, Aug 16, 2016 at 02:40:43PM +, Zhengyu Shen wrote:
> > > Added cpumask and migration handling support to driver
> > > Validated event during event_init
> > > Added code to properly stop counters
> > > Used perf_invalid_context instead of perf_sw_context
> > > Added hrtimer to
On Mon, Aug 15, 2016 at 05:50:50PM +0100, Mark Rutland wrote:
> For the Nth time, I'm going to say that really, we should have the core check
> this (or expose helpers to do so). It's somewhat ridiculous that evry driver
> has to blacklist everything it doesn't support, rather than whitelisting
On Mon, Aug 15, 2016 at 05:50:50PM +0100, Mark Rutland wrote:
> For the Nth time, I'm going to say that really, we should have the core check
> this (or expose helpers to do so). It's somewhat ridiculous that evry driver
> has to blacklist everything it doesn't support, rather than whitelisting
Hi,
On Mon, Aug 15, 2016 at 05:30:35PM -0500, Zhengyu Shen wrote:
> MMDC is a multi-mode DDR controller that supports DDR3/DDR3L x16/x32/x64 and
> LPDDR2 two channel x16/x32 memory types. MMDC is configurable, high
> performance,
> and optimized. MMDC is present on i.MX6 Quad and i.MX6 QuadPlus
Hi,
On Mon, Aug 15, 2016 at 05:30:35PM -0500, Zhengyu Shen wrote:
> MMDC is a multi-mode DDR controller that supports DDR3/DDR3L x16/x32/x64 and
> LPDDR2 two channel x16/x32 memory types. MMDC is configurable, high
> performance,
> and optimized. MMDC is present on i.MX6 Quad and i.MX6 QuadPlus
Hi Zhengyu,
[auto build test ERROR on shawnguo/for-next]
[also build test ERROR on v4.8-rc2 next-20160815]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
Hi Zhengyu,
[auto build test ERROR on shawnguo/for-next]
[also build test ERROR on v4.8-rc2 next-20160815]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
MMDC is a multi-mode DDR controller that supports DDR3/DDR3L x16/x32/x64 and
LPDDR2 two channel x16/x32 memory types. MMDC is configurable, high performance,
and optimized. MMDC is present on i.MX6 Quad and i.MX6 QuadPlus devices, but
this driver only supports i.MX6 Quad at the moment. MMDC
MMDC is a multi-mode DDR controller that supports DDR3/DDR3L x16/x32/x64 and
LPDDR2 two channel x16/x32 memory types. MMDC is configurable, high performance,
and optimized. MMDC is present on i.MX6 Quad and i.MX6 QuadPlus devices, but
this driver only supports i.MX6 Quad at the moment. MMDC
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