Re: [PATCH v2] x86/amd: Derive L3 shared_cpu_map from cpu_llc_shared_mask

2017-07-29 Thread Borislav Petkov
On Thu, Jul 27, 2017 at 08:52:35PM -0500, Suravee Suthikulpanit wrote: > For system with X86_FEATURE_TOPOEXT, current logic use APIC ID to > calculate shared_cpu_map. However, since APIC IDs are not guaranteed > to be contiguous for cores across different L3 (e.g. family17h system > w/ downcore

Re: [PATCH v2] x86/amd: Derive L3 shared_cpu_map from cpu_llc_shared_mask

2017-07-29 Thread Borislav Petkov
On Thu, Jul 27, 2017 at 08:52:35PM -0500, Suravee Suthikulpanit wrote: > For system with X86_FEATURE_TOPOEXT, current logic use APIC ID to > calculate shared_cpu_map. However, since APIC IDs are not guaranteed > to be contiguous for cores across different L3 (e.g. family17h system > w/ downcore

[PATCH v2] x86/amd: Derive L3 shared_cpu_map from cpu_llc_shared_mask

2017-07-27 Thread Suravee Suthikulpanit
For system with X86_FEATURE_TOPOEXT, current logic use APIC ID to calculate shared_cpu_map. However, since APIC IDs are not guaranteed to be contiguous for cores across different L3 (e.g. family17h system w/ downcore configuration). This breaks the logic, and results in incorrect L3

[PATCH v2] x86/amd: Derive L3 shared_cpu_map from cpu_llc_shared_mask

2017-07-27 Thread Suravee Suthikulpanit
For system with X86_FEATURE_TOPOEXT, current logic use APIC ID to calculate shared_cpu_map. However, since APIC IDs are not guaranteed to be contiguous for cores across different L3 (e.g. family17h system w/ downcore configuration). This breaks the logic, and results in incorrect L3