On Tue, 2018-10-02 at 09:44 +0200, Peter Zijlstra wrote:
> On Tue, Sep 25, 2018 at 11:58:37PM -0400, Rik van Riel wrote:
>
> > This v2 is "identical" to the version I posted yesterday,
> > except this one is actually against current -tip (not sure
> > what went wrong before), with a number of
On Tue, 2018-10-02 at 09:44 +0200, Peter Zijlstra wrote:
> On Tue, Sep 25, 2018 at 11:58:37PM -0400, Rik van Riel wrote:
>
> > This v2 is "identical" to the version I posted yesterday,
> > except this one is actually against current -tip (not sure
> > what went wrong before), with a number of
On Tue, Sep 25, 2018 at 11:58:37PM -0400, Rik van Riel wrote:
> This v2 is "identical" to the version I posted yesterday,
> except this one is actually against current -tip (not sure
> what went wrong before), with a number of relevant patches
> on top:
> - tip x86/core
> 012e77a903d
On Tue, Sep 25, 2018 at 11:58:37PM -0400, Rik van Riel wrote:
> This v2 is "identical" to the version I posted yesterday,
> except this one is actually against current -tip (not sure
> what went wrong before), with a number of relevant patches
> on top:
> - tip x86/core
> 012e77a903d
Looks good to me,
Acked-by: Peter Zijlstra (Intel)
Looks good to me,
Acked-by: Peter Zijlstra (Intel)
Linus asked me to come up with a smaller patch set to get the benefits
of lazy TLB mode, so I spent some time trying out various permutations
of the code, with a few workloads that do lots of context switches, and
also happen to have a fair number of TLB flushes a second.
Both of the workloads
Linus asked me to come up with a smaller patch set to get the benefits
of lazy TLB mode, so I spent some time trying out various permutations
of the code, with a few workloads that do lots of context switches, and
also happen to have a fair number of TLB flushes a second.
Both of the workloads
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