Add coherency_max_size variable to record the maximum cache line size for different cache levels. We will synchronize it with CTR_EL0.CWG reporting in cache_line_size() for arm64.
Cc: Greg Kroah-Hartman <gre...@linuxfoundation.org> Cc: "Rafael J. Wysocki" <raf...@kernel.org> Cc: Sudeep Holla <sudeep.ho...@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com> Cc: Jeremy Linton <jeremy.lin...@arm.com> Cc: Will Deacon <will.dea...@arm.com> Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com> --- ChangeLog since v1 -- Move coherency_max_size to drivers/base/cacheinfo.c -- Address Catalin's comments Link: https://www.spinics.net/lists/arm-kernel/msg723615.html drivers/base/cacheinfo.c | 5 +++++ include/linux/cacheinfo.h | 2 ++ 2 files changed, 7 insertions(+) diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c index a7359535caf5..8827c60f51e2 100644 --- a/drivers/base/cacheinfo.c +++ b/drivers/base/cacheinfo.c @@ -213,6 +213,8 @@ int __weak cache_setup_acpi(unsigned int cpu) return -ENOTSUPP; } +unsigned int coherency_max_size; + static int cache_shared_cpu_map_setup(unsigned int cpu) { struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); @@ -251,6 +253,9 @@ static int cache_shared_cpu_map_setup(unsigned int cpu) cpumask_set_cpu(i, &this_leaf->shared_cpu_map); } } + /* record the maximum cache line size */ + if (this_leaf->coherency_line_size > coherency_max_size) + coherency_max_size = this_leaf->coherency_line_size; } return 0; diff --git a/include/linux/cacheinfo.h b/include/linux/cacheinfo.h index 70e19bc6cc9f..46b92cd61d0c 100644 --- a/include/linux/cacheinfo.h +++ b/include/linux/cacheinfo.h @@ -17,6 +17,8 @@ enum cache_type { CACHE_TYPE_UNIFIED = BIT(2), }; +extern unsigned int coherency_max_size; + /** * struct cacheinfo - represent a cache leaf node * @id: This cache's id. It is unique among caches with the same (type, level). -- 2.7.4
