On Tue, Jun 09, 2015 at 07:06:14PM +0200, Borislav Petkov wrote:
> On Tue, Jun 09, 2015 at 09:44:59AM -0700, Andy Lutomirski wrote:
> > [1] For those who weren't bitten by this repeatedly, modern Intel CPUs
> > (at least Sandy Bridge, anyway) will, by default, detect when all
> > cores are in C1
On Tue, Jun 09, 2015 at 09:44:59AM -0700, Andy Lutomirski wrote:
> [1] For those who weren't bitten by this repeatedly, modern Intel CPUs
> (at least Sandy Bridge, anyway) will, by default, detect when all
> cores are in C1 or deeper, think to themselves "wow, the OS selected
> C1 -- it must want
On Jun 9, 2015 3:05 AM, "Borislav Petkov" wrote:
>
> On Tue, Jun 09, 2015 at 05:48:56PM +0800, Huang Rui wrote:
> > Any better suggestion? EBX * (TSC cycle) ? :)
>
> No, he means to put the description of MWAITX, what registers it
> uses/takes and so on over __mwaitx() and not only in the commit
On Tue, Jun 09, 2015 at 05:48:56PM +0800, Huang Rui wrote:
> Any better suggestion? EBX * (TSC cycle) ? :)
No, he means to put the description of MWAITX, what registers it
uses/takes and so on over __mwaitx() and not only in the commit message.
--
Regards/Gruss,
Boris.
ECO tip #101: Trim
On Tue, Jun 09, 2015 at 04:23:06PM +0800, Peter Zijlstra wrote:
> On Tue, Jun 09, 2015 at 11:13:38AM +0800, Huang Rui wrote:
> >
> > MWAITX ECX[1]: enable timer if set
> > MWAITX EBX[31:0]: max wait time expressed in SW P0 clocks
> >
> > The software P0 frequency is the same as the TSC
On Tue, Jun 09, 2015 at 11:13:38AM +0800, Huang Rui wrote:
>
> MWAITX ECX[1]: enable timer if set
> MWAITX EBX[31:0]: max wait time expressed in SW P0 clocks
>
> The software P0 frequency is the same as the TSC frequency.
>
> Max timeout = EBX/(TSC frequency)
^ that, would make a lovely
On Tue, Jun 09, 2015 at 04:23:06PM +0800, Peter Zijlstra wrote:
On Tue, Jun 09, 2015 at 11:13:38AM +0800, Huang Rui wrote:
MWAITX ECX[1]: enable timer if set
MWAITX EBX[31:0]: max wait time expressed in SW P0 clocks
The software P0 frequency is the same as the TSC frequency.
Max
On Tue, Jun 09, 2015 at 05:48:56PM +0800, Huang Rui wrote:
Any better suggestion? EBX * (TSC cycle) ? :)
No, he means to put the description of MWAITX, what registers it
uses/takes and so on over __mwaitx() and not only in the commit message.
--
Regards/Gruss,
Boris.
ECO tip #101: Trim
On Tue, Jun 09, 2015 at 11:13:38AM +0800, Huang Rui wrote:
MWAITX ECX[1]: enable timer if set
MWAITX EBX[31:0]: max wait time expressed in SW P0 clocks
The software P0 frequency is the same as the TSC frequency.
Max timeout = EBX/(TSC frequency)
^ that, would make a lovely comment for
On Jun 9, 2015 3:05 AM, Borislav Petkov b...@suse.de wrote:
On Tue, Jun 09, 2015 at 05:48:56PM +0800, Huang Rui wrote:
Any better suggestion? EBX * (TSC cycle) ? :)
No, he means to put the description of MWAITX, what registers it
uses/takes and so on over __mwaitx() and not only in the
On Tue, Jun 09, 2015 at 09:44:59AM -0700, Andy Lutomirski wrote:
[1] For those who weren't bitten by this repeatedly, modern Intel CPUs
(at least Sandy Bridge, anyway) will, by default, detect when all
cores are in C1 or deeper, think to themselves wow, the OS selected
C1 -- it must want a
On Tue, Jun 09, 2015 at 07:06:14PM +0200, Borislav Petkov wrote:
On Tue, Jun 09, 2015 at 09:44:59AM -0700, Andy Lutomirski wrote:
[1] For those who weren't bitten by this repeatedly, modern Intel CPUs
(at least Sandy Bridge, anyway) will, by default, detect when all
cores are in C1 or
On AMD Carrizo processors (Family 15h, Model 60h-6fh), there is a new
feature called MWAITT (Mwait with a timer) as an extension of
Monitor/Mwait.
MWAITT, another name is MWAITX (MWAIT with extensions), has a configurable
timer that causes MWAITX to exit on expiration.
Compared with
On AMD Carrizo processors (Family 15h, Model 60h-6fh), there is a new
feature called MWAITT (Mwait with a timer) as an extension of
Monitor/Mwait.
MWAITT, another name is MWAITX (MWAIT with extensions), has a configurable
timer that causes MWAITX to exit on expiration.
Compared with
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