On Mon, Jun 20, 2016 at 03:50:07PM -0400, Paul Gortmaker wrote:
> On Mon, May 9, 2016 at 7:49 AM, Niklas Cassel wrote:
> > From: Niklas Cassel
> >
> > The Axis ARTPEC-6 SoC integrates a PCIe controller from Synopsys.
> > This commit adds a new
On Mon, Jun 20, 2016 at 03:50:07PM -0400, Paul Gortmaker wrote:
> On Mon, May 9, 2016 at 7:49 AM, Niklas Cassel wrote:
> > From: Niklas Cassel
> >
> > The Axis ARTPEC-6 SoC integrates a PCIe controller from Synopsys.
> > This commit adds a new driver that provides the small glue
> > needed to
On Mon, May 9, 2016 at 7:49 AM, Niklas Cassel wrote:
> From: Niklas Cassel
>
> The Axis ARTPEC-6 SoC integrates a PCIe controller from Synopsys.
> This commit adds a new driver that provides the small glue
> needed to use the existing Designware
On Mon, May 9, 2016 at 7:49 AM, Niklas Cassel wrote:
> From: Niklas Cassel
>
> The Axis ARTPEC-6 SoC integrates a PCIe controller from Synopsys.
> This commit adds a new driver that provides the small glue
> needed to use the existing Designware driver to make it work on
> the Axis ARTPEC-6 SoC.
On Mon, Jun 20, 2016 at 02:56:58AM +0200, Niklas Cassel wrote:
>
> On 06/13/2016 03:33 PM, Bjorn Helgaas wrote:
> > On Mon, Jun 13, 2016 at 03:12:13PM +0200, Niklas Cassel wrote:
> >> On 06/10/2016 12:41 AM, Bjorn Helgaas wrote:
> >>> On Mon, May 09, 2016 at 01:49:03PM +0200, Niklas Cassel wrote:
On Mon, Jun 20, 2016 at 02:56:58AM +0200, Niklas Cassel wrote:
>
> On 06/13/2016 03:33 PM, Bjorn Helgaas wrote:
> > On Mon, Jun 13, 2016 at 03:12:13PM +0200, Niklas Cassel wrote:
> >> On 06/10/2016 12:41 AM, Bjorn Helgaas wrote:
> >>> On Mon, May 09, 2016 at 01:49:03PM +0200, Niklas Cassel wrote:
On 06/13/2016 03:33 PM, Bjorn Helgaas wrote:
> On Mon, Jun 13, 2016 at 03:12:13PM +0200, Niklas Cassel wrote:
>> On 06/10/2016 12:41 AM, Bjorn Helgaas wrote:
>>> On Mon, May 09, 2016 at 01:49:03PM +0200, Niklas Cassel wrote:
From: Niklas Cassel
The Axis
On 06/13/2016 03:33 PM, Bjorn Helgaas wrote:
> On Mon, Jun 13, 2016 at 03:12:13PM +0200, Niklas Cassel wrote:
>> On 06/10/2016 12:41 AM, Bjorn Helgaas wrote:
>>> On Mon, May 09, 2016 at 01:49:03PM +0200, Niklas Cassel wrote:
From: Niklas Cassel
The Axis ARTPEC-6 SoC integrates a
On Mon, Jun 13, 2016 at 03:12:13PM +0200, Niklas Cassel wrote:
> On 06/10/2016 12:41 AM, Bjorn Helgaas wrote:
> > On Mon, May 09, 2016 at 01:49:03PM +0200, Niklas Cassel wrote:
> >> From: Niklas Cassel
> >>
> >> The Axis ARTPEC-6 SoC integrates a PCIe controller from
On Mon, Jun 13, 2016 at 03:12:13PM +0200, Niklas Cassel wrote:
> On 06/10/2016 12:41 AM, Bjorn Helgaas wrote:
> > On Mon, May 09, 2016 at 01:49:03PM +0200, Niklas Cassel wrote:
> >> From: Niklas Cassel
> >>
> >> The Axis ARTPEC-6 SoC integrates a PCIe controller from Synopsys.
> >> This commit
On 06/10/2016 12:41 AM, Bjorn Helgaas wrote:
> On Mon, May 09, 2016 at 01:49:03PM +0200, Niklas Cassel wrote:
>> From: Niklas Cassel
>>
>> The Axis ARTPEC-6 SoC integrates a PCIe controller from Synopsys.
>> This commit adds a new driver that provides the small glue
>>
On 06/10/2016 12:41 AM, Bjorn Helgaas wrote:
> On Mon, May 09, 2016 at 01:49:03PM +0200, Niklas Cassel wrote:
>> From: Niklas Cassel
>>
>> The Axis ARTPEC-6 SoC integrates a PCIe controller from Synopsys.
>> This commit adds a new driver that provides the small glue
>> needed to use the existing
On Mon, May 09, 2016 at 01:49:03PM +0200, Niklas Cassel wrote:
> From: Niklas Cassel
>
> The Axis ARTPEC-6 SoC integrates a PCIe controller from Synopsys.
> This commit adds a new driver that provides the small glue
> needed to use the existing Designware driver to make
On Mon, May 09, 2016 at 01:49:03PM +0200, Niklas Cassel wrote:
> From: Niklas Cassel
>
> The Axis ARTPEC-6 SoC integrates a PCIe controller from Synopsys.
> This commit adds a new driver that provides the small glue
> needed to use the existing Designware driver to make it work on
> the Axis
From: Niklas Cassel
The Axis ARTPEC-6 SoC integrates a PCIe controller from Synopsys.
This commit adds a new driver that provides the small glue
needed to use the existing Designware driver to make it work on
the Axis ARTPEC-6 SoC.
Signed-off-by: Niklas Cassel
From: Niklas Cassel
The Axis ARTPEC-6 SoC integrates a PCIe controller from Synopsys.
This commit adds a new driver that provides the small glue
needed to use the existing Designware driver to make it work on
the Axis ARTPEC-6 SoC.
Signed-off-by: Niklas Cassel
---
Changes since v1:
- Rename
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