On Mon, Jul 30, 2018 at 8:30 AM, Keiji Hayashibara
wrote:
> Hello Trent and Andy,
>> > > + ckrat = roundup(ckrat, 2);
>> >
>> > ckrat += ckrat & 1;
>>
>> Either way, the compiler produces the same code:
>>
>> add r0, r0, #1
>> bic r0, r0, #1
>>
>> I.e., ckrat = (ckrat + 1) & ~1, one
On Mon, Jul 30, 2018 at 8:30 AM, Keiji Hayashibara
wrote:
> Hello Trent and Andy,
>> > > + ckrat = roundup(ckrat, 2);
>> >
>> > ckrat += ckrat & 1;
>>
>> Either way, the compiler produces the same code:
>>
>> add r0, r0, #1
>> bic r0, r0, #1
>>
>> I.e., ckrat = (ckrat + 1) & ~1, one
Hello Trent and Andy,
> From: Trent Piepho [mailto:tpie...@impinj.com]
> Sent: Friday, July 27, 2018 2:02 AM
> To: andy.shevche...@gmail.com; Hayashibara, Keiji/林原 啓二
>
> Subject: Re: [PATCH v2 2/2] spi: add SPI controller driver for UniPhier SoC
>
> On Thu, 2018-07-26
Hello Trent and Andy,
> From: Trent Piepho [mailto:tpie...@impinj.com]
> Sent: Friday, July 27, 2018 2:02 AM
> To: andy.shevche...@gmail.com; Hayashibara, Keiji/林原 啓二
>
> Subject: Re: [PATCH v2 2/2] spi: add SPI controller driver for UniPhier SoC
>
> On Thu, 2018-07-26
> Rutland ;
> Yamada, Masahiro/山田 真弘 ; linux-spi
> ; linux-arm
> Mailing List ; devicetree
> ; Masami Hiramatsu
> ; Jassi Brar ; Linux
> Kernel Mailing List
> ; Hayashi, Kunihiko/林 邦彦
>
> Subject: Re: [PATCH v2 2/2] spi: add SPI controller driver for UniPhi
> Rutland ;
> Yamada, Masahiro/山田 真弘 ; linux-spi
> ; linux-arm
> Mailing List ; devicetree
> ; Masami Hiramatsu
> ; Jassi Brar ; Linux
> Kernel Mailing List
> ; Hayashi, Kunihiko/林 邦彦
>
> Subject: Re: [PATCH v2 2/2] spi: add SPI controller driver for UniPhi
Hello Radu,
> From: Radu Pirea [mailto:radu.pi...@microchip.com]
> Sent: Thursday, July 26, 2018 7:58 PM
> To: Hayashibara, Keiji/林原 啓二 ; 'Andy
> Shevchenko'
>
> Subject: Re: [PATCH v2 2/2] spi: add SPI controller driver for UniPhier SoC
>
>
>
> On 07/26/20
Hello Radu,
> From: Radu Pirea [mailto:radu.pi...@microchip.com]
> Sent: Thursday, July 26, 2018 7:58 PM
> To: Hayashibara, Keiji/林原 啓二 ; 'Andy
> Shevchenko'
>
> Subject: Re: [PATCH v2 2/2] spi: add SPI controller driver for UniPhier SoC
>
>
>
> On 07/26/20
On Thu, 2018-07-26 at 11:46 +0300, Andy Shevchenko wrote:
> > +
> > + /*
> > +* the supported rates are even numbers from 4 to 254. (4,6,8...254)
> > +* round up as we look for equal or less speed
> > +*/
> > + ckrat = DIV_ROUND_UP(clk_get_rate(priv->clk),
On Thu, 2018-07-26 at 11:46 +0300, Andy Shevchenko wrote:
> > +
> > + /*
> > +* the supported rates are even numbers from 4 to 254. (4,6,8...254)
> > +* round up as we look for equal or less speed
> > +*/
> > + ckrat = DIV_ROUND_UP(clk_get_rate(priv->clk),
On Thu, Jul 26, 2018 at 12:38 PM, Keiji Hayashibara
wrote:
>> > + /* check if requested speed is too small */
>> > + if (ckrat > SSI_MAX_CLK_DIVIDER)
>>
>> > + return -EINVAL;
>>
>> So, does this critical?
>
> If set the value to SSI_MAX_CLK_DIVIDER, the clock frequency
On Thu, Jul 26, 2018 at 12:38 PM, Keiji Hayashibara
wrote:
>> > + /* check if requested speed is too small */
>> > + if (ckrat > SSI_MAX_CLK_DIVIDER)
>>
>> > + return -EINVAL;
>>
>> So, does this critical?
>
> If set the value to SSI_MAX_CLK_DIVIDER, the clock frequency
On 07/26/2018 12:38 PM, Keiji Hayashibara wrote:
Hello Andy,
Thank you for your check!
From: Andy Shevchenko [mailto:andy.shevche...@gmail.com]
Sent: Thursday, July 26, 2018 5:46 PM
To: Hayashibara, Keiji/林原 啓二
Subject: Re: [PATCH v2 2/2] spi: add SPI controller driver for UniPhier SoC
On 07/26/2018 12:38 PM, Keiji Hayashibara wrote:
Hello Andy,
Thank you for your check!
From: Andy Shevchenko [mailto:andy.shevche...@gmail.com]
Sent: Thursday, July 26, 2018 5:46 PM
To: Hayashibara, Keiji/林原 啓二
Subject: Re: [PATCH v2 2/2] spi: add SPI controller driver for UniPhier SoC
Hello Yamada-san,
> From: Masahiro Yamada [mailto:yamada.masah...@socionext.com]
> Sent: Thursday, July 26, 2018 6:13 PM
> To: Hayashibara, Keiji/林原 啓二
> Subject: Re: [PATCH v2 2/2] spi: add SPI controller driver for UniPhier SoC
>
> Hi.
>
>
> 2018-07-26 16:09
Hello Yamada-san,
> From: Masahiro Yamada [mailto:yamada.masah...@socionext.com]
> Sent: Thursday, July 26, 2018 6:13 PM
> To: Hayashibara, Keiji/林原 啓二
> Subject: Re: [PATCH v2 2/2] spi: add SPI controller driver for UniPhier SoC
>
> Hi.
>
>
> 2018-07-26 16:09
Hello Andy,
Thank you for your check!
> From: Andy Shevchenko [mailto:andy.shevche...@gmail.com]
> Sent: Thursday, July 26, 2018 5:46 PM
> To: Hayashibara, Keiji/林原 啓二
> Subject: Re: [PATCH v2 2/2] spi: add SPI controller driver for UniPhier SoC
>
> On Thu, Jul 26, 2018
Hello Andy,
Thank you for your check!
> From: Andy Shevchenko [mailto:andy.shevche...@gmail.com]
> Sent: Thursday, July 26, 2018 5:46 PM
> To: Hayashibara, Keiji/林原 啓二
> Subject: Re: [PATCH v2 2/2] spi: add SPI controller driver for UniPhier SoC
>
> On Thu, Jul 26, 2018
Hi.
2018-07-26 16:09 GMT+09:00 Keiji Hayashibara :
> Add SPI controller driver implemented in Socionext UniPhier SoCs.
>
> UniPhier SoCs have two types SPI controllers; SCSSI supports a
> single channel, and MCSSI supports multiple channels.
> This driver supports SCSSI only.
>
> This controller
Hi.
2018-07-26 16:09 GMT+09:00 Keiji Hayashibara :
> Add SPI controller driver implemented in Socionext UniPhier SoCs.
>
> UniPhier SoCs have two types SPI controllers; SCSSI supports a
> single channel, and MCSSI supports multiple channels.
> This driver supports SCSSI only.
>
> This controller
On Thu, Jul 26, 2018 at 10:09 AM, Keiji Hayashibara
wrote:
> Add SPI controller driver implemented in Socionext UniPhier SoCs.
>
> UniPhier SoCs have two types SPI controllers; SCSSI supports a
> single channel, and MCSSI supports multiple channels.
> This driver supports SCSSI only.
>
> This
On Thu, Jul 26, 2018 at 10:09 AM, Keiji Hayashibara
wrote:
> Add SPI controller driver implemented in Socionext UniPhier SoCs.
>
> UniPhier SoCs have two types SPI controllers; SCSSI supports a
> single channel, and MCSSI supports multiple channels.
> This driver supports SCSSI only.
>
> This
Add SPI controller driver implemented in Socionext UniPhier SoCs.
UniPhier SoCs have two types SPI controllers; SCSSI supports a
single channel, and MCSSI supports multiple channels.
This driver supports SCSSI only.
This controller has 32bit TX/RX FIFO with depth of eight entry,
and supports the
Add SPI controller driver implemented in Socionext UniPhier SoCs.
UniPhier SoCs have two types SPI controllers; SCSSI supports a
single channel, and MCSSI supports multiple channels.
This driver supports SCSSI only.
This controller has 32bit TX/RX FIFO with depth of eight entry,
and supports the
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