On 10/28, Will Deacon wrote:
>
> Sure. There's a spelling mistake ("arhitecture") which you should fix,
> but the code looks ok.
Ok I'll fix it up and send it off to the patch tracker if I don't
hear anything else.
> >
> > I have an RFC for the undef handler written up, except for the
> >
On Mon, Oct 27, 2014 at 07:50:42PM +, Stephen Boyd wrote:
> On 10/27/2014 03:31 AM, Will Deacon wrote:
> > On Tue, Oct 14, 2014 at 02:48:58PM +0100, Stephen Boyd wrote:
> >> If the CPU is using CPUID scheme, use the MVFR registers to
> >> determine what version of VFP is supported. We already
On Mon, Oct 27, 2014 at 07:50:42PM +, Stephen Boyd wrote:
On 10/27/2014 03:31 AM, Will Deacon wrote:
On Tue, Oct 14, 2014 at 02:48:58PM +0100, Stephen Boyd wrote:
If the CPU is using CPUID scheme, use the MVFR registers to
determine what version of VFP is supported. We already do this
On 10/28, Will Deacon wrote:
Sure. There's a spelling mistake (arhitecture) which you should fix,
but the code looks ok.
Ok I'll fix it up and send it off to the patch tracker if I don't
hear anything else.
I have an RFC for the undef handler written up, except for the
big/little
On 10/27/2014 03:31 AM, Will Deacon wrote:
> Hi Stephen,
>
> On Tue, Oct 14, 2014 at 02:48:58PM +0100, Stephen Boyd wrote:
>> The subarchitecture field in the fpsid register is 7 bits wide on
>> ARM CPUs using the CPUID identification scheme, spanning bits 22
>> to 16. The topmost bit is used to
Will Deacon writes:
> Perhaps it would be better to consider exposing the ID registers to
> userspace in some manner? This could be done either via an undef handler, or
> using the vdso. We would add a (final) hwcap advertising this cpuid support.
> For big/little systems, the kernel would need
Hi Stephen,
On Tue, Oct 14, 2014 at 02:48:58PM +0100, Stephen Boyd wrote:
> The subarchitecture field in the fpsid register is 7 bits wide on
> ARM CPUs using the CPUID identification scheme, spanning bits 22
> to 16. The topmost bit is used to designate that the
> subarchitecture designer is not
Hi Stephen,
On Tue, Oct 14, 2014 at 02:48:58PM +0100, Stephen Boyd wrote:
The subarchitecture field in the fpsid register is 7 bits wide on
ARM CPUs using the CPUID identification scheme, spanning bits 22
to 16. The topmost bit is used to designate that the
subarchitecture designer is not ARM
Will Deacon will.dea...@arm.com writes:
Perhaps it would be better to consider exposing the ID registers to
userspace in some manner? This could be done either via an undef handler, or
using the vdso. We would add a (final) hwcap advertising this cpuid support.
For big/little systems, the
On 10/27/2014 03:31 AM, Will Deacon wrote:
Hi Stephen,
On Tue, Oct 14, 2014 at 02:48:58PM +0100, Stephen Boyd wrote:
The subarchitecture field in the fpsid register is 7 bits wide on
ARM CPUs using the CPUID identification scheme, spanning bits 22
to 16. The topmost bit is used to designate
The subarchitecture field in the fpsid register is 7 bits wide on
ARM CPUs using the CPUID identification scheme, spanning bits 22
to 16. The topmost bit is used to designate that the
subarchitecture designer is not ARM when it is set to 1. On
non-CPUID scheme CPUs the subarchitecture field is
The subarchitecture field in the fpsid register is 7 bits wide on
ARM CPUs using the CPUID identification scheme, spanning bits 22
to 16. The topmost bit is used to designate that the
subarchitecture designer is not ARM when it is set to 1. On
non-CPUID scheme CPUs the subarchitecture field is
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