* Some lines exceeded 80 characters.
* Clarified statement about AUX register interface
Signed-off-by: Mischa Jonker <mischa.jon...@synopsys.com>
---
.../bindings/interrupt-controller/snps,archs-idu-intc.txt | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt
b/Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt
index 09fc02b..c5a1c7b 100644
---
a/Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt
+++
b/Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt
@@ -1,7 +1,8 @@
* ARC-HS Interrupt Distribution Unit
- This optional 2nd level interrupt controller can be used in SMP
configurations for
- dynamic IRQ routing, load balancing of common/external IRQs towards core
intc.
+ This optional 2nd level interrupt controller can be used in SMP
configurations
+ for dynamic IRQ routing, load balancing of common/external IRQs towards core
+ intc.
Properties:
@@ -13,8 +14,8 @@ Properties:
of the particular interrupt line of IDU corresponds to the line N+24 of the
core interrupt controller.
- intc accessed via the special ARC AUX register interface, hence "reg"
property
- is not specified.
+ The interrupt controller is accessed via the special ARC AUX register
+ interface, hence "reg" property is not specified.
Example:
core_intc: core-interrupt-controller {
--
2.8.3
