On 09/02/2016 01:14 PM, Shawn Lin wrote:
> We could see an obvious race condition by test that
> the former write operation by IDMAC aiming to clear
> OWN bit reach right after the later configuration of
> the same desc, which makes the IDMAC be in SUSPEND
> state as the OWN bit was cleared by the
在 2016/9/20 17:49, Jaehoon Chung 写道:
Hi Shawn,
On 09/20/2016 06:47 PM, Shawn Lin wrote:
Hi Jaehoon,
Friendly ping... :)
Thanks for reminding! :) I forgot your patch-set..sorry!
Ah, never mind, I just want to make sure if I still need
to update it.:)
Best Regards,
Jaehoon Chung
On 201
Hi Shawn,
On 09/20/2016 06:47 PM, Shawn Lin wrote:
> Hi Jaehoon,
>
> Friendly ping... :)
Thanks for reminding! :) I forgot your patch-set..sorry!
Best Regards,
Jaehoon Chung
>
> On 2016/9/2 12:14, Shawn Lin wrote:
>> We could see an obvious race condition by test that
>> the former write opera
Hi Jaehoon,
Friendly ping... :)
On 2016/9/2 12:14, Shawn Lin wrote:
We could see an obvious race condition by test that
the former write operation by IDMAC aiming to clear
OWN bit reach right after the later configuration of
the same desc, which makes the IDMAC be in SUSPEND
state as the OWN bi
We could see an obvious race condition by test that
the former write operation by IDMAC aiming to clear
OWN bit reach right after the later configuration of
the same desc, which makes the IDMAC be in SUSPEND
state as the OWN bit was cleared by the asynchronous
write operation of IDMAC. The bug can
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