Re: [RESEND PATCH v2 2/5] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

2017-09-22 Thread Vignesh R
On Friday 22 September 2017 01:34 PM, kbuild test robot wrote: > Hi Vignesh, > > [auto build test WARNING on l2-mtd-boris/spi-nor/next] > [also build test WARNING on v4.14-rc1 next-20170921] > [if your patch is applied to the wrong git tree, please drop us a note to > help improve the system]

Re: [RESEND PATCH v2 2/5] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

2017-09-22 Thread Vignesh R
On Friday 22 September 2017 01:34 PM, kbuild test robot wrote: > Hi Vignesh, > > [auto build test WARNING on l2-mtd-boris/spi-nor/next] > [also build test WARNING on v4.14-rc1 next-20170921] > [if your patch is applied to the wrong git tree, please drop us a note to > help improve the system]

Re: [RESEND PATCH v2 2/5] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

2017-09-22 Thread kbuild test robot
Hi Vignesh, [auto build test WARNING on l2-mtd-boris/spi-nor/next] [also build test WARNING on v4.14-rc1 next-20170921] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url:

Re: [RESEND PATCH v2 2/5] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

2017-09-22 Thread kbuild test robot
Hi Vignesh, [auto build test WARNING on l2-mtd-boris/spi-nor/next] [also build test WARNING on v4.14-rc1 next-20170921] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url:

[RESEND PATCH v2 2/5] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

2017-09-19 Thread Vignesh R
As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access Controller programming sequence, a delay equal to couple of QSPI master clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and writing data to the flash. Introduce a quirk flag CQSPI_NEEDS_WR_DELAY to handle this

[RESEND PATCH v2 2/5] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

2017-09-19 Thread Vignesh R
As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access Controller programming sequence, a delay equal to couple of QSPI master clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and writing data to the flash. Introduce a quirk flag CQSPI_NEEDS_WR_DELAY to handle this

[PATCH v2 2/5] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

2017-08-15 Thread Vignesh R
As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access Controller programming sequence, a delay equal to couple of QSPI master clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and writing data to the flash. Introduce a quirk flag CQSPI_NEEDS_WR_DELAY to handle this

[PATCH v2 2/5] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

2017-08-15 Thread Vignesh R
As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access Controller programming sequence, a delay equal to couple of QSPI master clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and writing data to the flash. Introduce a quirk flag CQSPI_NEEDS_WR_DELAY to handle this