On Wed, Apr 30, 2014 at 1:00 AM, Robert Richter wrote:
> On 29.04.14 15:40:28, Myron Stowe wrote:
>> On Tue, Apr 29, 2014 at 1:14 PM, Borislav Petkov wrote:
>> > So sounds to me like we want to get rid of the whole IO ECS deal
>> > altogether then.
>> >
>> > Now, I'm wondering whether we should
On 30.04.14 02:50:21, Suravee Suthikulpanit wrote:
> Actually, if ECS is needed by IBS, then wouldn't this still be needed for
> every family since 10h and later (except family11h).
Yes, but you have stated that pci mmconfig should work on families >
10h. Thus, ECS would work there out-of-the-box
On 04/30/2014 02:00 AM, Robert Richter wrote:
On 29.04.14 15:40:28, Myron Stowe wrote:
On Tue, Apr 29, 2014 at 1:14 PM, Borislav Petkov wrote:
So sounds to me like we want to get rid of the whole IO ECS deal
altogether then.
Now, I'm wondering whether we should kill it completely since I
On 29.04.14 15:40:28, Myron Stowe wrote:
> On Tue, Apr 29, 2014 at 1:14 PM, Borislav Petkov wrote:
> > So sounds to me like we want to get rid of the whole IO ECS deal
> > altogether then.
> >
> > Now, I'm wondering whether we should kill it completely since I don't
> > think anyone cares about
On 18.04.14 20:53:23, Myron Stowe wrote:
> From: Suravee Suthikulpanit
> - start = reg & 0xff00; /* 39:16 on 31:8*/
> - start <<= 8;
> - reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
> + start = (reg & 0xff00UL) << 8; /* 39:16
On 18.04.14 20:53:23, Myron Stowe wrote:
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
- start = reg 0xff00; /* 39:16 on 31:8*/
- start = 8;
- reg = read_pci_config(bus, slot, 1, 0x84 + (i 3));
+ start = (reg 0xff00UL)
On 29.04.14 15:40:28, Myron Stowe wrote:
On Tue, Apr 29, 2014 at 1:14 PM, Borislav Petkov b...@alien8.de wrote:
So sounds to me like we want to get rid of the whole IO ECS deal
altogether then.
Now, I'm wondering whether we should kill it completely since I don't
think anyone cares
On 04/30/2014 02:00 AM, Robert Richter wrote:
On 29.04.14 15:40:28, Myron Stowe wrote:
On Tue, Apr 29, 2014 at 1:14 PM, Borislav Petkov b...@alien8.de wrote:
So sounds to me like we want to get rid of the whole IO ECS deal
altogether then.
Now, I'm wondering whether we should kill it
On 30.04.14 02:50:21, Suravee Suthikulpanit wrote:
Actually, if ECS is needed by IBS, then wouldn't this still be needed for
every family since 10h and later (except family11h).
Yes, but you have stated that pci mmconfig should work on families
10h. Thus, ECS would work there out-of-the-box
On Wed, Apr 30, 2014 at 1:00 AM, Robert Richter r...@kernel.org wrote:
On 29.04.14 15:40:28, Myron Stowe wrote:
On Tue, Apr 29, 2014 at 1:14 PM, Borislav Petkov b...@alien8.de wrote:
So sounds to me like we want to get rid of the whole IO ECS deal
altogether then.
Now, I'm wondering
On Tue, Apr 29, 2014 at 1:14 PM, Borislav Petkov wrote:
> On Tue, Apr 29, 2014 at 10:16:57AM -0500, Suravee Suthikulanit wrote:
>> In the new code, the IO ECS was needed to retrieve the
>> AMD_NB_F1_MMIO_BASE_LIMIT_HI_REG (offset 0x180) during the early
>> initialization as part of (2) logic.
On Tue, Apr 29, 2014 at 10:16:57AM -0500, Suravee Suthikulanit wrote:
> In the new code, the IO ECS was needed to retrieve the
> AMD_NB_F1_MMIO_BASE_LIMIT_HI_REG (offset 0x180) during the early
> initialization as part of (2) logic. However, this register exists only on
> the newer systems.
In addition to Boris I have the following:
On 18.04.14 20:53:23, Myron Stowe wrote:
> +#define AMD_PCIE_CF8(bus, dev, fn, reg) \
> + (0x8000 | \
> + ((reg & 0xF00) << 16) | \
> + ((bus & 0xF) << 16) | \
> + ((dev
On 4/29/2014 5:20 AM, Borislav Petkov wrote:
On Tue, Apr 29, 2014 at 09:33:09AM +0200, Andreas Herrmann wrote:
I am sure, it's because some server systems had MMIO ECS access not
enabled in BIOS. I can't remember which systems were affected.
If you are referring to accessing PCI ECS ranges
On 29 Apr 2014, at 3:20 , Borislav Petkov wrote:
> On Tue, Apr 29, 2014 at 09:33:09AM +0200, Andreas Herrmann wrote:
>> I am sure, it's because some server systems had MMIO ECS access not
>> enabled in BIOS. I can't remember which systems were affected.
>
> Ok, now AMD people: what's the story
On 29.04.14 09:33:09, Andreas Herrmann wrote:
> On Mon, Apr 28, 2014 at 11:40:36PM +0200, Borislav Petkov wrote:
> > On Mon, Apr 28, 2014 at 02:50:29PM -0600, Bjorn Helgaas wrote:
> > > This I/O ECS thing seems likely to cause future problems. My
> > > understanding (based on sec 2.8 of [1]) is
On Tue, Apr 29, 2014 at 09:33:09AM +0200, Andreas Herrmann wrote:
> I am sure, it's because some server systems had MMIO ECS access not
> enabled in BIOS. I can't remember which systems were affected.
Ok, now AMD people: what's the story with IO ECS, can we assume that on
everything after F10h,
On Mon, Apr 28, 2014 at 11:40:36PM +0200, Borislav Petkov wrote:
> On Mon, Apr 28, 2014 at 02:50:29PM -0600, Bjorn Helgaas wrote:
> > This I/O ECS thing seems likely to cause future problems. My
> > understanding (based on sec 2.8 of [1]) is that enable_pci_io_ecs()
> > and
>>> On 28.04.14 at 22:50, wrote:
>>> > There's a enable_pci_io_ecs() which enables ECS through the NB_CFG MSR
>>> > which is called as part of the notifier *and* there's a PCI write to
>>> > that same bit in pci_enable_pci_io_ecs() which iterates over all NBs.
>>> >
>>> > So, AFAICT, we do it
On 28.04.14 at 22:50, bhelg...@google.com wrote:
There's a enable_pci_io_ecs() which enables ECS through the NB_CFG MSR
which is called as part of the notifier *and* there's a PCI write to
that same bit in pci_enable_pci_io_ecs() which iterates over all NBs.
So, AFAICT, we do it twice
On Mon, Apr 28, 2014 at 11:40:36PM +0200, Borislav Petkov wrote:
On Mon, Apr 28, 2014 at 02:50:29PM -0600, Bjorn Helgaas wrote:
This I/O ECS thing seems likely to cause future problems. My
understanding (based on sec 2.8 of [1]) is that enable_pci_io_ecs()
and pci_enable_pci_io_ecs() are
On Tue, Apr 29, 2014 at 09:33:09AM +0200, Andreas Herrmann wrote:
I am sure, it's because some server systems had MMIO ECS access not
enabled in BIOS. I can't remember which systems were affected.
Ok, now AMD people: what's the story with IO ECS, can we assume that on
everything after F10h,
On 29.04.14 09:33:09, Andreas Herrmann wrote:
On Mon, Apr 28, 2014 at 11:40:36PM +0200, Borislav Petkov wrote:
On Mon, Apr 28, 2014 at 02:50:29PM -0600, Bjorn Helgaas wrote:
This I/O ECS thing seems likely to cause future problems. My
understanding (based on sec 2.8 of [1]) is that
On 29 Apr 2014, at 3:20 , Borislav Petkov b...@suse.de wrote:
On Tue, Apr 29, 2014 at 09:33:09AM +0200, Andreas Herrmann wrote:
I am sure, it's because some server systems had MMIO ECS access not
enabled in BIOS. I can't remember which systems were affected.
Ok, now AMD people: what's the
On 4/29/2014 5:20 AM, Borislav Petkov wrote:
On Tue, Apr 29, 2014 at 09:33:09AM +0200, Andreas Herrmann wrote:
I am sure, it's because some server systems had MMIO ECS access not
enabled in BIOS. I can't remember which systems were affected.
If you are referring to accessing PCI ECS ranges
In addition to Boris I have the following:
On 18.04.14 20:53:23, Myron Stowe wrote:
+#define AMD_PCIE_CF8(bus, dev, fn, reg) \
+ (0x8000 | \
+ ((reg 0xF00) 16) | \
+ ((bus 0xF) 16) | \
+ ((dev 0x1F) 11)
On Tue, Apr 29, 2014 at 10:16:57AM -0500, Suravee Suthikulanit wrote:
In the new code, the IO ECS was needed to retrieve the
AMD_NB_F1_MMIO_BASE_LIMIT_HI_REG (offset 0x180) during the early
initialization as part of (2) logic. However, this register exists only on
the newer systems. However,
On Tue, Apr 29, 2014 at 1:14 PM, Borislav Petkov b...@alien8.de wrote:
On Tue, Apr 29, 2014 at 10:16:57AM -0500, Suravee Suthikulanit wrote:
In the new code, the IO ECS was needed to retrieve the
AMD_NB_F1_MMIO_BASE_LIMIT_HI_REG (offset 0x180) during the early
initialization as part of (2)
On 4/25/2014 5:24 PM, Myron Stowe wrote:
On Sun, Apr 20, 2014 at 1:59 AM, Borislav Petkov wrote:
Drop Andreas' old email address from CC as it keeps bouncing.
On Sat, Apr 19, 2014 at 03:52:20PM +0200, Borislav Petkov wrote:
-static void __init pci_enable_pci_io_ecs(void)
+static void __init
On 4/28/2014 4:19 PM, Myron Stowe wrote:
On Sat, Apr 19, 2014 at 7:52 AM, Borislav Petkov wrote:
On Fri, Apr 18, 2014 at 08:53:23PM -0600, Myron Stowe wrote:
From: Suravee Suthikulpanit
...
@@ -118,6 +154,12 @@ static int __init early_fill_mp_bus_info(void)
pr_debug("Found
On Mon, Apr 28, 2014 at 02:50:29PM -0600, Bjorn Helgaas wrote:
> This I/O ECS thing seems likely to cause future problems. My
> understanding (based on sec 2.8 of [1]) is that enable_pci_io_ecs()
> and pci_enable_pci_io_ecs() are there to enable access to extended
> config space (offsets
On Sat, Apr 19, 2014 at 7:52 AM, Borislav Petkov wrote:
> On Fri, Apr 18, 2014 at 08:53:23PM -0600, Myron Stowe wrote:
>> From: Suravee Suthikulpanit
>>
>> This patch adds supports for additional MMIO ranges (16 ranges). Also,
>> each MMIO base/limit can now support up to 48-bit MMIO addresses.
[+cc Jan (24d9b70b8 author), Yinghai]
On Sat, Apr 26, 2014 at 3:10 AM, Borislav Petkov wrote:
> + Robert.
>
> On Fri, Apr 25, 2014 at 04:24:31PM -0600, Myron Stowe wrote:
>> On Sun, Apr 20, 2014 at 1:59 AM, Borislav Petkov wrote:
>> > Drop Andreas' old email address from CC as it keeps
[+cc Jan (24d9b70b8 author), Yinghai]
On Sat, Apr 26, 2014 at 3:10 AM, Borislav Petkov b...@suse.de wrote:
+ Robert.
On Fri, Apr 25, 2014 at 04:24:31PM -0600, Myron Stowe wrote:
On Sun, Apr 20, 2014 at 1:59 AM, Borislav Petkov b...@suse.de wrote:
Drop Andreas' old email address from CC as
On Sat, Apr 19, 2014 at 7:52 AM, Borislav Petkov b...@alien8.de wrote:
On Fri, Apr 18, 2014 at 08:53:23PM -0600, Myron Stowe wrote:
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
This patch adds supports for additional MMIO ranges (16 ranges). Also,
each MMIO base/limit can now
On Mon, Apr 28, 2014 at 02:50:29PM -0600, Bjorn Helgaas wrote:
This I/O ECS thing seems likely to cause future problems. My
understanding (based on sec 2.8 of [1]) is that enable_pci_io_ecs()
and pci_enable_pci_io_ecs() are there to enable access to extended
config space (offsets 256-4095)
On 4/28/2014 4:19 PM, Myron Stowe wrote:
On Sat, Apr 19, 2014 at 7:52 AM, Borislav Petkov b...@alien8.de wrote:
On Fri, Apr 18, 2014 at 08:53:23PM -0600, Myron Stowe wrote:
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
...
@@ -118,6 +154,12 @@ static int __init
On 4/25/2014 5:24 PM, Myron Stowe wrote:
On Sun, Apr 20, 2014 at 1:59 AM, Borislav Petkov b...@suse.de wrote:
Drop Andreas' old email address from CC as it keeps bouncing.
On Sat, Apr 19, 2014 at 03:52:20PM +0200, Borislav Petkov wrote:
-static void __init pci_enable_pci_io_ecs(void)
+static
+ Robert.
On Fri, Apr 25, 2014 at 04:24:31PM -0600, Myron Stowe wrote:
> On Sun, Apr 20, 2014 at 1:59 AM, Borislav Petkov wrote:
> > Drop Andreas' old email address from CC as it keeps bouncing.
> >
> > On Sat, Apr 19, 2014 at 03:52:20PM +0200, Borislav Petkov wrote:
> >> > -static void __init
+ Robert.
On Fri, Apr 25, 2014 at 04:24:31PM -0600, Myron Stowe wrote:
On Sun, Apr 20, 2014 at 1:59 AM, Borislav Petkov b...@suse.de wrote:
Drop Andreas' old email address from CC as it keeps bouncing.
On Sat, Apr 19, 2014 at 03:52:20PM +0200, Borislav Petkov wrote:
-static void __init
On Sun, Apr 20, 2014 at 1:59 AM, Borislav Petkov wrote:
> Drop Andreas' old email address from CC as it keeps bouncing.
>
> On Sat, Apr 19, 2014 at 03:52:20PM +0200, Borislav Petkov wrote:
>> > -static void __init pci_enable_pci_io_ecs(void)
>> > +static void __init pci_enable_pci_io_ecs(u8 bus,
On Sun, Apr 20, 2014 at 1:59 AM, Borislav Petkov b...@suse.de wrote:
Drop Andreas' old email address from CC as it keeps bouncing.
On Sat, Apr 19, 2014 at 03:52:20PM +0200, Borislav Petkov wrote:
-static void __init pci_enable_pci_io_ecs(void)
+static void __init pci_enable_pci_io_ecs(u8
Drop Andreas' old email address from CC as it keeps bouncing.
On Sat, Apr 19, 2014 at 03:52:20PM +0200, Borislav Petkov wrote:
> > -static void __init pci_enable_pci_io_ecs(void)
> > +static void __init pci_enable_pci_io_ecs(u8 bus, u8 slot)
> > {
> > #ifdef CONFIG_AMD_NB
> > unsigned int
Drop Andreas' old email address from CC as it keeps bouncing.
On Sat, Apr 19, 2014 at 03:52:20PM +0200, Borislav Petkov wrote:
-static void __init pci_enable_pci_io_ecs(void)
+static void __init pci_enable_pci_io_ecs(u8 bus, u8 slot)
{
#ifdef CONFIG_AMD_NB
unsigned int i, n;
+
On Fri, Apr 18, 2014 at 08:53:23PM -0600, Myron Stowe wrote:
> From: Suravee Suthikulpanit
>
> This patch adds supports for additional MMIO ranges (16 ranges). Also,
> each MMIO base/limit can now support up to 48-bit MMIO addresses.
> However, this requires initializing the ECS sooner since
On Fri, Apr 18, 2014 at 08:53:23PM -0600, Myron Stowe wrote:
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
This patch adds supports for additional MMIO ranges (16 ranges). Also,
each MMIO base/limit can now support up to 48-bit MMIO addresses.
However, this requires initializing
From: Suravee Suthikulpanit
This patch adds supports for additional MMIO ranges (16 ranges). Also,
each MMIO base/limit can now support up to 48-bit MMIO addresses.
However, this requires initializing the ECS sooner since the new registers
are in the ECS ranges.
This applies for AMD Family 15h
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
This patch adds supports for additional MMIO ranges (16 ranges). Also,
each MMIO base/limit can now support up to 48-bit MMIO addresses.
However, this requires initializing the ECS sooner since the new registers
are in the ECS ranges.
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