On 07/07/17 14:12, Jassi Brar wrote:
> On Fri, Jul 7, 2017 at 5:02 PM, Sudeep Holla wrote:
>>
>>
>> On 06/07/17 19:37, Jassi Brar wrote:
>>> On Thu, Jul 6, 2017 at 10:14 PM, Sudeep Holla wrote:
On 06/07/17 15:37, Jassi Brar wrote:
> On
On 07/07/17 14:12, Jassi Brar wrote:
> On Fri, Jul 7, 2017 at 5:02 PM, Sudeep Holla wrote:
>>
>>
>> On 06/07/17 19:37, Jassi Brar wrote:
>>> On Thu, Jul 6, 2017 at 10:14 PM, Sudeep Holla wrote:
On 06/07/17 15:37, Jassi Brar wrote:
> On Thu, Jul 6, 2017 at 3:03 PM, Sudeep Holla
On Fri, Jul 7, 2017 at 5:02 PM, Sudeep Holla wrote:
>
>
> On 06/07/17 19:37, Jassi Brar wrote:
>> On Thu, Jul 6, 2017 at 10:14 PM, Sudeep Holla wrote:
>>>
>>> On 06/07/17 15:37, Jassi Brar wrote:
On Thu, Jul 6, 2017 at 3:03 PM, Sudeep Holla
On Fri, Jul 7, 2017 at 5:02 PM, Sudeep Holla wrote:
>
>
> On 06/07/17 19:37, Jassi Brar wrote:
>> On Thu, Jul 6, 2017 at 10:14 PM, Sudeep Holla wrote:
>>>
>>> On 06/07/17 15:37, Jassi Brar wrote:
On Thu, Jul 6, 2017 at 3:03 PM, Sudeep Holla wrote:
>>>
>>
I see no reason why you must
On 06/07/17 19:37, Jassi Brar wrote:
> On Thu, Jul 6, 2017 at 10:14 PM, Sudeep Holla wrote:
>>
>> On 06/07/17 15:37, Jassi Brar wrote:
>>> On Thu, Jul 6, 2017 at 3:03 PM, Sudeep Holla wrote:
>>
>
>>> I see no reason why you must have SCPI and SCMI
On 06/07/17 19:37, Jassi Brar wrote:
> On Thu, Jul 6, 2017 at 10:14 PM, Sudeep Holla wrote:
>>
>> On 06/07/17 15:37, Jassi Brar wrote:
>>> On Thu, Jul 6, 2017 at 3:03 PM, Sudeep Holla wrote:
>>
>
>>> I see no reason why you must have SCPI and SCMI both running.
>>>
>>
>> We can still have 2
On Thu, Jul 6, 2017 at 10:14 PM, Sudeep Holla wrote:
>
> On 06/07/17 15:37, Jassi Brar wrote:
>> On Thu, Jul 6, 2017 at 3:03 PM, Sudeep Holla wrote:
>
>> I see no reason why you must have SCPI and SCMI both running.
>>
>
> We can still have 2
On Thu, Jul 6, 2017 at 10:14 PM, Sudeep Holla wrote:
>
> On 06/07/17 15:37, Jassi Brar wrote:
>> On Thu, Jul 6, 2017 at 3:03 PM, Sudeep Holla wrote:
>
>> I see no reason why you must have SCPI and SCMI both running.
>>
>
> We can still have 2 different protocols using same MHU channel with
>
On 06/07/17 15:37, Jassi Brar wrote:
> On Thu, Jul 6, 2017 at 3:03 PM, Sudeep Holla wrote:
[...]
>>
>> I said it *may not be used*, currently it is used.
>>
> SCPI provides more than what SCMI currently does - dvfs, clock, sensor.
Not sure what you mean by that, but
On 06/07/17 15:37, Jassi Brar wrote:
> On Thu, Jul 6, 2017 at 3:03 PM, Sudeep Holla wrote:
[...]
>>
>> I said it *may not be used*, currently it is used.
>>
> SCPI provides more than what SCMI currently does - dvfs, clock, sensor.
Not sure what you mean by that, but that's not true.
> I see
On Thu, Jul 6, 2017 at 3:03 PM, Sudeep Holla wrote:
>
>
> On 06/07/17 10:27, Jassi Brar wrote:
>> On Thu, Jul 6, 2017 at 2:48 PM, Sudeep Holla wrote:
>>> Hi Jassi,
>>>
>>> On 06/07/17 07:28, Jassi Brar wrote:
On Wed, Jul 5, 2017 at 11:32 PM,
On Thu, Jul 6, 2017 at 3:03 PM, Sudeep Holla wrote:
>
>
> On 06/07/17 10:27, Jassi Brar wrote:
>> On Thu, Jul 6, 2017 at 2:48 PM, Sudeep Holla wrote:
>>> Hi Jassi,
>>>
>>> On 06/07/17 07:28, Jassi Brar wrote:
On Wed, Jul 5, 2017 at 11:32 PM, Sudeep Holla wrote:
>
> I have
On 06/07/17 10:27, Jassi Brar wrote:
> On Thu, Jul 6, 2017 at 2:48 PM, Sudeep Holla wrote:
>> Hi Jassi,
>>
>> On 06/07/17 07:28, Jassi Brar wrote:
>>> On Wed, Jul 5, 2017 at 11:32 PM, Sudeep Holla wrote:
>>>
I have posted the SCMI patches
On 06/07/17 10:27, Jassi Brar wrote:
> On Thu, Jul 6, 2017 at 2:48 PM, Sudeep Holla wrote:
>> Hi Jassi,
>>
>> On 06/07/17 07:28, Jassi Brar wrote:
>>> On Wed, Jul 5, 2017 at 11:32 PM, Sudeep Holla wrote:
>>>
I have posted the SCMI patches now[1],
>>> I wish I was CC'ed on that.
On Thu, Jul 6, 2017 at 2:48 PM, Sudeep Holla wrote:
> Hi Jassi,
>
> On 06/07/17 07:28, Jassi Brar wrote:
>> On Wed, Jul 5, 2017 at 11:32 PM, Sudeep Holla wrote:
>>
>>>
>>> I have posted the SCMI patches now[1],
>>>
>> I wish I was CC'ed on that. Now
On Thu, Jul 6, 2017 at 2:48 PM, Sudeep Holla wrote:
> Hi Jassi,
>
> On 06/07/17 07:28, Jassi Brar wrote:
>> On Wed, Jul 5, 2017 at 11:32 PM, Sudeep Holla wrote:
>>
>>>
>>> I have posted the SCMI patches now[1],
>>>
>> I wish I was CC'ed on that. Now LKML seems too busy to forward it.
>>
>
> Yes,
Hi Jassi,
On 06/07/17 07:28, Jassi Brar wrote:
> On Wed, Jul 5, 2017 at 11:32 PM, Sudeep Holla wrote:
>
>>
>> I have posted the SCMI patches now[1],
>>
> I wish I was CC'ed on that. Now LKML seems too busy to forward it.
>
Yes, my mistake, I should have cc-ed you.
>>
Hi Jassi,
On 06/07/17 07:28, Jassi Brar wrote:
> On Wed, Jul 5, 2017 at 11:32 PM, Sudeep Holla wrote:
>
>>
>> I have posted the SCMI patches now[1],
>>
> I wish I was CC'ed on that. Now LKML seems too busy to forward it.
>
Yes, my mistake, I should have cc-ed you.
>> please let me know how
On Wed, Jul 5, 2017 at 11:32 PM, Sudeep Holla wrote:
>
> I have posted the SCMI patches now[1],
>
I wish I was CC'ed on that. Now LKML seems too busy to forward it.
> please let me know how to get
> both SCPI and SCMI working together with different doorbell bits on the
>
On Wed, Jul 5, 2017 at 11:32 PM, Sudeep Holla wrote:
>
> I have posted the SCMI patches now[1],
>
I wish I was CC'ed on that. Now LKML seems too busy to forward it.
> please let me know how to get
> both SCPI and SCMI working together with different doorbell bits on the
> same channel.
>
You
On 02/06/17 10:32, Sudeep Holla wrote:
>
>
> On 02/06/17 06:45, Jassi Brar wrote:
>> Hi Rob,
>>
>> On Wed, May 31, 2017 at 10:38 PM, Rob Herring wrote:
>>> On Thu, May 25, 2017 at 02:23:44PM +0100, Sudeep Holla wrote:
>> .../devicetree/bindings/mailbox/arm-mhu.txt
On 02/06/17 10:32, Sudeep Holla wrote:
>
>
> On 02/06/17 06:45, Jassi Brar wrote:
>> Hi Rob,
>>
>> On Wed, May 31, 2017 at 10:38 PM, Rob Herring wrote:
>>> On Thu, May 25, 2017 at 02:23:44PM +0100, Sudeep Holla wrote:
>> .../devicetree/bindings/mailbox/arm-mhu.txt| 46
On 02/06/17 06:45, Jassi Brar wrote:
> Hi Rob,
>
> On Wed, May 31, 2017 at 10:38 PM, Rob Herring wrote:
>> On Thu, May 25, 2017 at 02:23:44PM +0100, Sudeep Holla wrote:
>>>
> .../devicetree/bindings/mailbox/arm-mhu.txt| 46
> --
> 1
On 02/06/17 06:45, Jassi Brar wrote:
> Hi Rob,
>
> On Wed, May 31, 2017 at 10:38 PM, Rob Herring wrote:
>> On Thu, May 25, 2017 at 02:23:44PM +0100, Sudeep Holla wrote:
>>>
> .../devicetree/bindings/mailbox/arm-mhu.txt| 46
> --
> 1 file changed, 43
Hi Rob,
On Wed, May 31, 2017 at 10:38 PM, Rob Herring wrote:
> On Thu, May 25, 2017 at 02:23:44PM +0100, Sudeep Holla wrote:
>>
>> >> .../devicetree/bindings/mailbox/arm-mhu.txt| 46
>> >> --
>> >> 1 file changed, 43 insertions(+), 3 deletions(-)
>>
Hi Rob,
On Wed, May 31, 2017 at 10:38 PM, Rob Herring wrote:
> On Thu, May 25, 2017 at 02:23:44PM +0100, Sudeep Holla wrote:
>>
>> >> .../devicetree/bindings/mailbox/arm-mhu.txt| 46
>> >> --
>> >> 1 file changed, 43 insertions(+), 3 deletions(-)
>> >>
>> >> diff
On 31/05/17 18:08, Rob Herring wrote:
> On Thu, May 25, 2017 at 02:23:44PM +0100, Sudeep Holla wrote:
>>
>>
>> On 25/05/17 14:22, Jassi Brar wrote:
[...]
>>> Every MHU controller can by driven as "arm,mhu-doorbell" or "arm,mhu"
>>> equally fine. So you are basically smuggling a s/w feature
On 31/05/17 18:08, Rob Herring wrote:
> On Thu, May 25, 2017 at 02:23:44PM +0100, Sudeep Holla wrote:
>>
>>
>> On 25/05/17 14:22, Jassi Brar wrote:
[...]
>>> Every MHU controller can by driven as "arm,mhu-doorbell" or "arm,mhu"
>>> equally fine. So you are basically smuggling a s/w feature
On Thu, May 25, 2017 at 02:23:44PM +0100, Sudeep Holla wrote:
>
>
> On 25/05/17 14:22, Jassi Brar wrote:
> > On Wed, May 24, 2017 at 3:46 PM, Sudeep Holla wrote:
> >> The ARM MHU has mechanism to assert interrupt signals to facilitate
> >> inter-processor message based
On Thu, May 25, 2017 at 02:23:44PM +0100, Sudeep Holla wrote:
>
>
> On 25/05/17 14:22, Jassi Brar wrote:
> > On Wed, May 24, 2017 at 3:46 PM, Sudeep Holla wrote:
> >> The ARM MHU has mechanism to assert interrupt signals to facilitate
> >> inter-processor message based communication. It drives
On 25/05/17 14:22, Jassi Brar wrote:
> On Wed, May 24, 2017 at 3:46 PM, Sudeep Holla wrote:
>> The ARM MHU has mechanism to assert interrupt signals to facilitate
>> inter-processor message based communication. It drives the signal using
>> a 32-bit register, with all
On 25/05/17 14:22, Jassi Brar wrote:
> On Wed, May 24, 2017 at 3:46 PM, Sudeep Holla wrote:
>> The ARM MHU has mechanism to assert interrupt signals to facilitate
>> inter-processor message based communication. It drives the signal using
>> a 32-bit register, with all 32-bits logically ORed
On 25/05/17 14:22, Jassi Brar wrote:
> On Wed, May 24, 2017 at 3:46 PM, Sudeep Holla wrote:
>> The ARM MHU has mechanism to assert interrupt signals to facilitate
>> inter-processor message based communication. It drives the signal using
>> a 32-bit register, with all
On 25/05/17 14:22, Jassi Brar wrote:
> On Wed, May 24, 2017 at 3:46 PM, Sudeep Holla wrote:
>> The ARM MHU has mechanism to assert interrupt signals to facilitate
>> inter-processor message based communication. It drives the signal using
>> a 32-bit register, with all 32-bits logically ORed
On Wed, May 24, 2017 at 3:46 PM, Sudeep Holla wrote:
> The ARM MHU has mechanism to assert interrupt signals to facilitate
> inter-processor message based communication. It drives the signal using
> a 32-bit register, with all 32-bits logically ORed together. It also
>
On Wed, May 24, 2017 at 3:46 PM, Sudeep Holla wrote:
> The ARM MHU has mechanism to assert interrupt signals to facilitate
> inter-processor message based communication. It drives the signal using
> a 32-bit register, with all 32-bits logically ORed together. It also
> enables software to set,
The ARM MHU has mechanism to assert interrupt signals to facilitate
inter-processor message based communication. It drives the signal using
a 32-bit register, with all 32-bits logically ORed together. It also
enables software to set, clear and check the status of each of the bits
of this register
The ARM MHU has mechanism to assert interrupt signals to facilitate
inter-processor message based communication. It drives the signal using
a 32-bit register, with all 32-bits logically ORed together. It also
enables software to set, clear and check the status of each of the bits
of this register
38 matches
Mail list logo