Re: [PATCH v2 2/8] cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devices

2021-04-13 Thread Dan Williams
On Tue, Apr 6, 2021 at 10:47 AM Jonathan Cameron wrote: > > On Thu, 1 Apr 2021 07:30:53 -0700 > Dan Williams wrote: > > > CXL MMIO register blocks are organized by device type and capabilities. > > There are Component registers, Device registers (yes, an ambiguous > > name), and Memory Device

Re: [PATCH v2 2/8] cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devices

2021-04-06 Thread Jonathan Cameron
On Thu, 1 Apr 2021 07:30:53 -0700 Dan Williams wrote: > CXL MMIO register blocks are organized by device type and capabilities. > There are Component registers, Device registers (yes, an ambiguous > name), and Memory Device registers (a specific extension of Device > registers). > > It is

[PATCH v2 2/8] cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devices

2021-04-01 Thread Dan Williams
CXL MMIO register blocks are organized by device type and capabilities. There are Component registers, Device registers (yes, an ambiguous name), and Memory Device registers (a specific extension of Device registers). It is possible for a given device instance (endpoint or port) to implement