Quoting Doug Anderson (2020-12-17 13:35:08)
>
> If we wanted to truly make this driver super robust against ridiculous
> interrupt latencies then, presumably, we could handle the SPI timeout
> ourselves but before timing out we could check to see if the
> interrupts were pending. Then we could di
Hi,
On Wed, Dec 16, 2020 at 8:29 PM Stephen Boyd wrote:
>
> > The SPI core in general assumes that setting chip select is a simple
> > operation that doesn't fail. Yet another reason to just reconfigure
> > the chip select line as GPIOs.
>
> BTW, we could peek at the irq bit for the CS change an
Hi,
On Wed, Dec 16, 2020 at 8:25 PM Stephen Boyd wrote:
>
> Quoting Douglas Anderson (2020-12-16 14:41:51)
> > If we get a timeout sending then this happens:
> > * spi_transfer_wait() will get a timeout.
> > * We'll set the chip select
> > * We'll call handle_err() => handle_fifo_timeout().
> >
>
On Wed, Dec 16, 2020 at 08:25:18PM -0800, Stephen Boyd wrote:
> > spin_lock_irq(&mas->lock);
> > + if (mas->cur_xfer) {
>
> How is it possible that cs change happens when cur_xfer is non-NULL?
We will set the initial chip select state during controller setup.
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Quoting Douglas Anderson (2020-12-16 14:41:51)
> If we get a timeout sending then this happens:
> * spi_transfer_wait() will get a timeout.
> * We'll set the chip select
> * We'll call handle_err() => handle_fifo_timeout().
>
> Unfortunately that won't work so well on geni. If we got a timeout
>
Quoting Douglas Anderson (2020-12-16 14:41:51)
> If we get a timeout sending then this happens:
> * spi_transfer_wait() will get a timeout.
> * We'll set the chip select
> * We'll call handle_err() => handle_fifo_timeout().
>
> Unfortunately that won't work so well on geni. If we got a timeout
>
If we get a timeout sending then this happens:
* spi_transfer_wait() will get a timeout.
* We'll set the chip select
* We'll call handle_err() => handle_fifo_timeout().
Unfortunately that won't work so well on geni. If we got a timeout
transferring then it's likely that our interrupt handler is b
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