On Fri, Jun 12, 2015 at 04:15:23PM -0700, Andy Lutomirski wrote:
> > How about this:
> >
> > /*
> > * This should be a memory location in a cache line which is
> > * unlikely to be touched by other processors. The actual
> > * content is immaterial as it is not a
On Jun 12, 2015 1:43 AM, "Borislav Petkov" wrote:
>
> On Tue, Jun 09, 2015 at 09:46:52AM -0700, Andy Lutomirski wrote:
> > I don't like this hack. The compiler is entirely within is rights to
> > poke addr's cacheline (i.e. the stack) between the two instructions.
> > I'd suggest either making th
On Tue, Jun 09, 2015 at 09:46:52AM -0700, Andy Lutomirski wrote:
> I don't like this hack. The compiler is entirely within is rights to
> poke addr's cacheline (i.e. the stack) between the two instructions.
> I'd suggest either making the thing a full cacheline long or using a
> single asm stateme
On Tue, Jun 9, 2015 at 11:43 AM, Borislav Petkov wrote:
> On Tue, Jun 09, 2015 at 10:55:15AM -0700, Andy Lutomirski wrote:
>> When I looked at the rdtsc ordering a couple years ago, I thought
>> about what it meant for rdtsc to be properly ordered. I decided that
>> proper rdtsc ordering meant th
On Tue, Jun 09, 2015 at 10:55:15AM -0700, Andy Lutomirski wrote:
> When I looked at the rdtsc ordering a couple years ago, I thought
> about what it meant for rdtsc to be properly ordered. I decided that
> proper rdtsc ordering meant that no one should ever be able to tell if
> rdtsc ends up reord
On Tue, Jun 9, 2015 at 10:13 AM, Peter Zijlstra wrote:
> On Tue, 2015-06-09 at 09:46 -0700, Andy Lutomirski wrote:
>> On Jun 9, 2015 2:30 AM, "Peter Zijlstra" wrote:
>
>> > How about you think instead and do something like:
>> >
>> > rdtsc(start);
>> > rdtsc_barrier();
>>
>> Other
On Tue, 2015-06-09 at 09:46 -0700, Andy Lutomirski wrote:
> On Jun 9, 2015 2:30 AM, "Peter Zijlstra" wrote:
> > How about you think instead and do something like:
> >
> > rdtsc(start);
> > rdtsc_barrier();
>
> Other way around. We really need a function static inline u64
> rdtsc
On Jun 9, 2015 2:30 AM, "Peter Zijlstra" wrote:
>
> On Tue, Jun 09, 2015 at 11:13:40AM +0800, Huang Rui wrote:
> > +static void delay_mwaitx(unsigned long __loops)
> > +{
> > + u32 end, now, delay, addr;
> > +
> > + delay = __loops;
> > + rdtsc_barrier();
> > + rdtscl(end);
> > +
On Tue, Jun 09, 2015 at 05:29:52PM +0800, Peter Zijlstra wrote:
> On Tue, Jun 09, 2015 at 11:13:40AM +0800, Huang Rui wrote:
> > +static void delay_mwaitx(unsigned long __loops)
> > +{
> > + u32 end, now, delay, addr;
> > +
> > + delay = __loops;
> > + rdtsc_barrier();
> > + rdtscl(end);
>
On Tue, Jun 09, 2015 at 04:31:03PM +0800, Peter Zijlstra wrote:
> On Tue, Jun 09, 2015 at 11:13:40AM +0800, Huang Rui wrote:
> > MWAITX can enable a timer and a corresponding timer value specified in SW
> > P0 clocks. The SW P0 frequency is the same with TSC. The timer provides an
> > upper bound o
On Tue, Jun 09, 2015 at 11:13:40AM +0800, Huang Rui wrote:
> +static void delay_mwaitx(unsigned long __loops)
> +{
> + u32 end, now, delay, addr;
> +
> + delay = __loops;
> + rdtsc_barrier();
> + rdtscl(end);
> + end += delay;
> +
> + while (1) {
> + __monitorx(&
On Tue, Jun 09, 2015 at 11:13:40AM +0800, Huang Rui wrote:
> MWAITX can enable a timer and a corresponding timer value specified in SW
> P0 clocks. The SW P0 frequency is the same with TSC. The timer provides an
> upper bound on how long the instruction waits before exiting.
>
> The implementation
MWAITX can enable a timer and a corresponding timer value specified in SW
P0 clocks. The SW P0 frequency is the same with TSC. The timer provides an
upper bound on how long the instruction waits before exiting.
The implementation of delay function in kernel can lerverage the timer of
MWAITX. This
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