Re: [PATCH v2 4/8] cxl/core: Refactor CXL register lookup for bridge reuse

2021-04-15 Thread Dan Williams
On Tue, Apr 6, 2021 at 10:47 AM Jonathan Cameron wrote: > > On Thu, 1 Apr 2021 07:31:03 -0700 > Dan Williams wrote: > > > While CXL Memory Device endpoints locate the CXL MMIO registers in a PCI > > BAR, CXL root bridges have their MMIO base address described by platform > > firmware. Refactor

Re: [PATCH v2 4/8] cxl/core: Refactor CXL register lookup for bridge reuse

2021-04-06 Thread Jonathan Cameron
On Thu, 1 Apr 2021 07:31:03 -0700 Dan Williams wrote: > While CXL Memory Device endpoints locate the CXL MMIO registers in a PCI > BAR, CXL root bridges have their MMIO base address described by platform > firmware. Refactor the existing register lookup into a generic facility > for endpoints

[PATCH v2 4/8] cxl/core: Refactor CXL register lookup for bridge reuse

2021-04-01 Thread Dan Williams
While CXL Memory Device endpoints locate the CXL MMIO registers in a PCI BAR, CXL root bridges have their MMIO base address described by platform firmware. Refactor the existing register lookup into a generic facility for endpoints and bridges to share. Reviewed-by: Ben Widawsky Signed-off-by: