On Tue, Apr 6, 2021 at 10:47 AM Jonathan Cameron
wrote:
>
> On Thu, 1 Apr 2021 07:31:03 -0700
> Dan Williams wrote:
>
> > While CXL Memory Device endpoints locate the CXL MMIO registers in a PCI
> > BAR, CXL root bridges have their MMIO base address described by platform
> > firmware. Refactor
On Thu, 1 Apr 2021 07:31:03 -0700
Dan Williams wrote:
> While CXL Memory Device endpoints locate the CXL MMIO registers in a PCI
> BAR, CXL root bridges have their MMIO base address described by platform
> firmware. Refactor the existing register lookup into a generic facility
> for endpoints
While CXL Memory Device endpoints locate the CXL MMIO registers in a PCI
BAR, CXL root bridges have their MMIO base address described by platform
firmware. Refactor the existing register lookup into a generic facility
for endpoints and bridges to share.
Reviewed-by: Ben Widawsky
Signed-off-by:
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