Re: [PATCH v2 5/7] pinctrl: aramda-37xx: Add irqchip support

Hi Linus, On mer., mars 29 2017, Linus Walleij wrote: >>> It has irq_create_mapping(gpiochip->irqdomain, offset); that get >>> called for every IRQ, and that will eventually call irq_of_parse_and_map() >>> if the IRQs are defined in the device tree. (IIRC) >> >> When

Re: [PATCH v2 5/7] pinctrl: aramda-37xx: Add irqchip support

Hi Linus, On mer., mars 29 2017, Linus Walleij wrote: >>> It has irq_create_mapping(gpiochip->irqdomain, offset); that get >>> called for every IRQ, and that will eventually call irq_of_parse_and_map() >>> if the IRQs are defined in the device tree. (IIRC) >> >> When I followed the functions

Re: [PATCH v2 5/7] pinctrl: aramda-37xx: Add irqchip support

On Tue, Mar 28, 2017 at 4:19 PM, Gregory CLEMENT wrote: > On mar., mars 28 2017, Linus Walleij wrote: >> What you're doing is mocking around with core irqchip semantics. >> Is ->mask really supposed to be played around with from the

Re: [PATCH v2 5/7] pinctrl: aramda-37xx: Add irqchip support

On Tue, Mar 28, 2017 at 4:19 PM, Gregory CLEMENT wrote: > On mar., mars 28 2017, Linus Walleij wrote: >> What you're doing is mocking around with core irqchip semantics. >> Is ->mask really supposed to be played around with from the outsid >> like this? > > According to the documentation mask

Re: [PATCH v2 5/7] pinctrl: aramda-37xx: Add irqchip support

Hi Linus, On mar., mars 28 2017, Linus Walleij wrote: > On Tue, Mar 28, 2017 at 12:36 PM, Gregory CLEMENT > wrote: >> On lun., mars 27 2017, Linus Walleij wrote: > + u32 virq

Re: [PATCH v2 5/7] pinctrl: aramda-37xx: Add irqchip support

Hi Linus, On mar., mars 28 2017, Linus Walleij wrote: > On Tue, Mar 28, 2017 at 12:36 PM, Gregory CLEMENT > wrote: >> On lun., mars 27 2017, Linus Walleij wrote: > + u32 virq = irq_linear_revmap(d, hwirq + +

Re: [PATCH v2 5/7] pinctrl: aramda-37xx: Add irqchip support

On Tue, Mar 28, 2017 at 12:36 PM, Gregory CLEMENT wrote: > On lun., mars 27 2017, Linus Walleij wrote: >>> + u32 virq = irq_linear_revmap(d, hwirq + >>> +i *

Re: [PATCH v2 5/7] pinctrl: aramda-37xx: Add irqchip support

On Tue, Mar 28, 2017 at 12:36 PM, Gregory CLEMENT wrote: > On lun., mars 27 2017, Linus Walleij wrote: >>> + u32 virq = irq_linear_revmap(d, hwirq + >>> +i * GPIO_PER_REG); >> >> Use irq_find_mapping() instead please. >

Re: [PATCH v2 5/7] pinctrl: aramda-37xx: Add irqchip support

Hi Linus, On lun., mars 27 2017, Linus Walleij wrote: > On Tue, Mar 21, 2017 at 7:28 PM, Gregory CLEMENT > wrote: > >> The Armada 37xx SoCs can handle interrupt through GPIO. However it can >> only manage the edge ones. >> >> The

Re: [PATCH v2 5/7] pinctrl: aramda-37xx: Add irqchip support

Hi Linus, On lun., mars 27 2017, Linus Walleij wrote: > On Tue, Mar 21, 2017 at 7:28 PM, Gregory CLEMENT > wrote: > >> The Armada 37xx SoCs can handle interrupt through GPIO. However it can >> only manage the edge ones. >> >> The way the interrupt are managed are classical so we can use the

Re: [PATCH v2 5/7] pinctrl: aramda-37xx: Add irqchip support

On Tue, Mar 21, 2017 at 7:28 PM, Gregory CLEMENT wrote: > The Armada 37xx SoCs can handle interrupt through GPIO. However it can > only manage the edge ones. > > The way the interrupt are managed are classical so we can use the generic > interrupt chip model.

Re: [PATCH v2 5/7] pinctrl: aramda-37xx: Add irqchip support

On Tue, Mar 21, 2017 at 7:28 PM, Gregory CLEMENT wrote: > The Armada 37xx SoCs can handle interrupt through GPIO. However it can > only manage the edge ones. > > The way the interrupt are managed are classical so we can use the generic > interrupt chip model. > > The only unusual "feature" is

[PATCH v2 5/7] pinctrl: aramda-37xx: Add irqchip support

The Armada 37xx SoCs can handle interrupt through GPIO. However it can only manage the edge ones. The way the interrupt are managed are classical so we can use the generic interrupt chip model. The only unusual "feature" is that many interrupts are connected to the parent interrupt controller.

[PATCH v2 5/7] pinctrl: aramda-37xx: Add irqchip support

The Armada 37xx SoCs can handle interrupt through GPIO. However it can only manage the edge ones. The way the interrupt are managed are classical so we can use the generic interrupt chip model. The only unusual "feature" is that many interrupts are connected to the parent interrupt controller.