Re: [PATCH v2 net-next v2 11/12] net: dsa: mv88e6xxx: add an SMI ops structure

2016-06-14 Thread Vivien Didelot
Hi Andrew, Andrew Lunn writes: >> +struct mv88e6xxx_smi_ops { >> +int (*read)(struct mii_bus *bus, int sw_addr, >> +int addr, int reg, u16 *val); >> +int (*write)(struct mii_bus *bus, int sw_addr, >> + int addr, int reg, u16 val); >> +};

Re: [PATCH v2 net-next v2 11/12] net: dsa: mv88e6xxx: add an SMI ops structure

2016-06-14 Thread Vivien Didelot
Hi Andrew, Andrew Lunn writes: >> +struct mv88e6xxx_smi_ops { >> +int (*read)(struct mii_bus *bus, int sw_addr, >> +int addr, int reg, u16 *val); >> +int (*write)(struct mii_bus *bus, int sw_addr, >> + int addr, int reg, u16 val); >> +}; >> + > > I think

Re: [PATCH v2 net-next v2 11/12] net: dsa: mv88e6xxx: add an SMI ops structure

2016-06-14 Thread Andrew Lunn
> +struct mv88e6xxx_smi_ops { > + int (*read)(struct mii_bus *bus, int sw_addr, > + int addr, int reg, u16 *val); > + int (*write)(struct mii_bus *bus, int sw_addr, > + int addr, int reg, u16 val); > +}; > + I think this API would be better if it used ps,

Re: [PATCH v2 net-next v2 11/12] net: dsa: mv88e6xxx: add an SMI ops structure

2016-06-14 Thread Andrew Lunn
> +struct mv88e6xxx_smi_ops { > + int (*read)(struct mii_bus *bus, int sw_addr, > + int addr, int reg, u16 *val); > + int (*write)(struct mii_bus *bus, int sw_addr, > + int addr, int reg, u16 val); > +}; > + I think this API would be better if it used ps,

[PATCH v2 net-next v2 11/12] net: dsa: mv88e6xxx: add an SMI ops structure

2016-06-14 Thread Vivien Didelot
The Marvell switch models have different mode the access the internal SMI registers. When the chip address on the SMI master bus is 0, the chips respond to all SMI devices addresses known to them. When the chip address is not zero, most chips use an indirect access to registers using two SMI

[PATCH v2 net-next v2 11/12] net: dsa: mv88e6xxx: add an SMI ops structure

2016-06-14 Thread Vivien Didelot
The Marvell switch models have different mode the access the internal SMI registers. When the chip address on the SMI master bus is 0, the chips respond to all SMI devices addresses known to them. When the chip address is not zero, most chips use an indirect access to registers using two SMI