[PATCH v21 3/7] x86/cet/ibt: Handle signals for Indirect Branch Tracking

[Yu-cheng Yu]

When an indirect CALL/JMP instruction is executed and before it reaches
the target, it is in 'WAIT_ENDBR' status, which can be read from
MSR_IA32_U_CET.  The status is part of a task's status before a signal is
raised and preserved in the signal frame.  It is restored for sigreturn.

IBT state machine is described in Intel SDM Vol. 1, Sec. 18.3.

Signed-off-by: Yu-cheng Yu <yu-cheng...@intel.com>
Reviewed-by: Kees Cook <keesc...@chromium.org>
---
 arch/x86/kernel/cet.c        | 26 ++++++++++++++++++++++++--
 arch/x86/kernel/fpu/signal.c |  8 +++++---
 2 files changed, 29 insertions(+), 5 deletions(-)

diff --git a/arch/x86/kernel/cet.c b/arch/x86/kernel/cet.c
index 3361706ba950..34a26eb7f259 100644
--- a/arch/x86/kernel/cet.c
+++ b/arch/x86/kernel/cet.c
@@ -300,6 +300,13 @@ void cet_restore_signal(struct sc_ext *sc_ext)
                msr_val |= CET_SHSTK_EN;
        }
 
+       if (cet->ibt_enabled) {
+               msr_val |= (CET_ENDBR_EN | CET_NO_TRACK_EN);
+
+               if (sc_ext->wait_endbr)
+                       msr_val |= CET_WAIT_ENDBR;
+       }
+
        if (test_thread_flag(TIF_NEED_FPU_LOAD))
                cet_user_state->user_cet = msr_val;
        else
@@ -340,9 +347,24 @@ int cet_setup_signal(bool ia32, unsigned long rstor_addr, 
struct sc_ext *sc_ext)
                sc_ext->ssp = new_ssp;
        }
 
-       if (ssp) {
+       if (ssp || cet->ibt_enabled) {
                start_update_msrs();
-               wrmsrl(MSR_IA32_PL3_SSP, ssp);
+
+               if (ssp)
+                       wrmsrl(MSR_IA32_PL3_SSP, ssp);
+
+               if (cet->ibt_enabled) {
+                       u64 r;
+
+                       rdmsrl(MSR_IA32_U_CET, r);
+
+                       if (r & CET_WAIT_ENDBR) {
+                               sc_ext->wait_endbr = 1;
+                               r &= ~CET_WAIT_ENDBR;
+                               wrmsrl(MSR_IA32_U_CET, r);
+                       }
+               }
+
                end_update_msrs();
        }
 
diff --git a/arch/x86/kernel/fpu/signal.c b/arch/x86/kernel/fpu/signal.c
index 270e4649f435..b914d74c8ba6 100644
--- a/arch/x86/kernel/fpu/signal.c
+++ b/arch/x86/kernel/fpu/signal.c
@@ -57,7 +57,8 @@ int save_cet_to_sigframe(int ia32, void __user *fp, unsigned 
long restorer)
 {
        int err = 0;
 
-       if (!current->thread.cet.shstk_size)
+       if (!current->thread.cet.shstk_size &&
+           !current->thread.cet.ibt_enabled)
                return 0;
 
        if (fp) {
@@ -89,7 +90,8 @@ static int get_cet_from_sigframe(int ia32, void __user *fp, 
struct sc_ext *ext)
 
        memset(ext, 0, sizeof(*ext));
 
-       if (!current->thread.cet.shstk_size)
+       if (!current->thread.cet.shstk_size &&
+           !current->thread.cet.ibt_enabled)
                return 0;
 
        if (fp) {
@@ -577,7 +579,7 @@ static unsigned long fpu__alloc_sigcontext_ext(unsigned 
long sp)
         * sigcontext_ext is at: fpu + fpu_user_xstate_size +
         * FP_XSTATE_MAGIC2_SIZE, then aligned to 8.
         */
-       if (cet->shstk_size)
+       if (cet->shstk_size || cet->ibt_enabled)
                sp -= (sizeof(struct sc_ext) + 8);
 
        return sp;
-- 
2.21.0