On Wed, Nov 5, 2014 at 4:42 PM, Lorenzo Pieralisi
wrote:
> On Wed, Nov 05, 2014 at 10:15:36AM +, Chander Kashyap wrote:
>> Exynos7 has core power down state where cores can be powered off
>> independently.
>> This patch adds support for this state.
>>
>> Entry latency for the core power down
On Wed, Nov 05, 2014 at 10:15:36AM +, Chander Kashyap wrote:
> Exynos7 has core power down state where cores can be powered off
> independently.
> This patch adds support for this state.
>
> Entry latency for the core power down is calculated as follows:
> 1. Time difference is measured
Exynos7 has core power down state where cores can be powered off independently.
This patch adds support for this state.
Entry latency for the core power down is calculated as follows:
1. Time difference is measured between cpuidle entry and exit.
2. WFI is skipped measuring the time.
3. The time
Exynos7 has core power down state where cores can be powered off independently.
This patch adds support for this state.
Entry latency for the core power down is calculated as follows:
1. Time difference is measured between cpuidle entry and exit.
2. WFI is skipped measuring the time.
3. The time
On Wed, Nov 05, 2014 at 10:15:36AM +, Chander Kashyap wrote:
Exynos7 has core power down state where cores can be powered off
independently.
This patch adds support for this state.
Entry latency for the core power down is calculated as follows:
1. Time difference is measured between
On Wed, Nov 5, 2014 at 4:42 PM, Lorenzo Pieralisi
lorenzo.pieral...@arm.com wrote:
On Wed, Nov 05, 2014 at 10:15:36AM +, Chander Kashyap wrote:
Exynos7 has core power down state where cores can be powered off
independently.
This patch adds support for this state.
Entry latency for the
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