Re: [PATCH v3] i2c: tegra: Create i2c_writesl_vi() to use with VI I2C for filling TX FIFO

2021-01-17 Thread Wolfram Sang
On Tue, Jan 12, 2021 at 11:02:41AM -0800, Sowjanya Komatineni wrote: > VI I2C controller has known hardware bug where immediate multiple > writes to TX_FIFO register gets stuck. > > Recommended software work around is to read I2C register after > each write to TX_FIFO register to flush out the dat

Re: [PATCH v3] i2c: tegra: Create i2c_writesl_vi() to use with VI I2C for filling TX FIFO

2021-01-15 Thread Thierry Reding
On Tue, Jan 12, 2021 at 11:02:41AM -0800, Sowjanya Komatineni wrote: > VI I2C controller has known hardware bug where immediate multiple > writes to TX_FIFO register gets stuck. > > Recommended software work around is to read I2C register after > each write to TX_FIFO register to flush out the dat

Re: [PATCH v3] i2c: tegra: Create i2c_writesl_vi() to use with VI I2C for filling TX FIFO

2021-01-12 Thread Dmitry Osipenko
12.01.2021 22:02, Sowjanya Komatineni пишет: > VI I2C controller has known hardware bug where immediate multiple > writes to TX_FIFO register gets stuck. > > Recommended software work around is to read I2C register after > each write to TX_FIFO register to flush out the data. > > This patch imple

[PATCH v3] i2c: tegra: Create i2c_writesl_vi() to use with VI I2C for filling TX FIFO

2021-01-12 Thread Sowjanya Komatineni
VI I2C controller has known hardware bug where immediate multiple writes to TX_FIFO register gets stuck. Recommended software work around is to read I2C register after each write to TX_FIFO register to flush out the data. This patch implements this work around for VI I2C controller. Signed-off-b