Re: [PATCH v3 0/2] riscv: sifive_l2_cache: Add support for SiFive FU740 SoC

2021-01-07 Thread Palmer Dabbelt
On Thu, 10 Dec 2020 02:28:01 PST (-0800), yash.s...@sifive.com wrote: Add support for additional interrupt present in SiFive FU740 chip. Changes: v3: - Rename the subject line of dt-binding patch - Add the additional interrupt "DirFail" as the last entry so as to keep the order of all previous

[PATCH v3 0/2] riscv: sifive_l2_cache: Add support for SiFive FU740 SoC

2020-12-10 Thread Yash Shah
Add support for additional interrupt present in SiFive FU740 chip. Changes: v3: - Rename the subject line of dt-binding patch - Add the additional interrupt "DirFail" as the last entry so as to keep the order of all previous index same. v2: - Changes as per Rob Herring's request on v1 Yash Sha