On Fri, May 22, 2020 at 08:03:25PM +0800, Feng Tang wrote:
> On Fri, May 22, 2020 at 02:32:35PM +0300, Serge Semin wrote:
> > On Fri, May 22, 2020 at 03:58:44PM +0800, Feng Tang wrote:
> > > Hi Serge,
> > >
> > > On Thu, May 21, 2020 at 06:33:17PM +0300, Serge Semin wrote:
> > > > > > > > +
On Fri, May 22, 2020 at 02:32:35PM +0300, Serge Semin wrote:
> On Fri, May 22, 2020 at 03:58:44PM +0800, Feng Tang wrote:
> > Hi Serge,
> >
> > On Thu, May 21, 2020 at 06:33:17PM +0300, Serge Semin wrote:
> > > > > > > + dw_spi_dma_wait_rx_done(dws);
> > > > > >
> > > > > > I can understand the
On Fri, May 22, 2020 at 03:58:44PM +0800, Feng Tang wrote:
> Hi Serge,
>
> On Thu, May 21, 2020 at 06:33:17PM +0300, Serge Semin wrote:
> > > > > > + dw_spi_dma_wait_rx_done(dws);
> > > > >
> > > > > I can understand the problem about TX, but I don't see how RX
> > > > > will get hurt, can you
Hi Serge,
On Thu, May 21, 2020 at 06:33:17PM +0300, Serge Semin wrote:
> > > > > + dw_spi_dma_wait_rx_done(dws);
> > > >
> > > > I can understand the problem about TX, but I don't see how RX
> > > > will get hurt, can you elaborate more? thanks
> > > >
> > > > - Feng
> > >
> > > Your
Mark, Andy,
On Thu, May 21, 2020 at 04:21:51AM +0300, Serge Semin wrote:
>
[nip]
> +static void dw_spi_dma_calc_delay(struct dw_spi *dws, u32 nents,
> + struct spi_delay *delay)
> +{
> + unsigned long ns, us;
> +
> + ns = (NSEC_PER_SEC / spi_get_clk(dws))
On Thu, May 21, 2020 at 10:55:20PM +0800, Feng Tang wrote:
> Hi Serge,
>
> On Thu, May 21, 2020 at 02:47:36PM +0300, Serge Semin wrote:
> > Hello Feng,
> >
> > On Thu, May 21, 2020 at 11:09:24AM +0800, Feng Tang wrote:
> > > Hi Serge,
> > >
> > > On Thu, May 21, 2020 at 04:21:51AM +0300, Serge
Hi Serge,
On Thu, May 21, 2020 at 02:47:36PM +0300, Serge Semin wrote:
> Hello Feng,
>
> On Thu, May 21, 2020 at 11:09:24AM +0800, Feng Tang wrote:
> > Hi Serge,
> >
> > On Thu, May 21, 2020 at 04:21:51AM +0300, Serge Semin wrote:
>
> [nip]
>
> > > /*
> > > * dws->dma_chan_busy is set
Hello Feng,
On Thu, May 21, 2020 at 11:09:24AM +0800, Feng Tang wrote:
> Hi Serge,
>
> On Thu, May 21, 2020 at 04:21:51AM +0300, Serge Semin wrote:
[nip]
> > /*
> > * dws->dma_chan_busy is set before the dma transfer starts, callback for
> > rx
> > * channel will clear a corresponding
Hi Serge,
On Thu, May 21, 2020 at 04:21:51AM +0300, Serge Semin wrote:
> Since DMA transfers are performed asynchronously with actual SPI
> transaction, then even if DMA transfers are finished it doesn't mean
> all data is actually pushed to the SPI bus. Some data might still be
> in the
Since DMA transfers are performed asynchronously with actual SPI
transaction, then even if DMA transfers are finished it doesn't mean
all data is actually pushed to the SPI bus. Some data might still be
in the controller FIFO. This is specifically true for Tx-only
transfers. In this case if the
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