[PATCH v3 06/20] clk: tegra: pll-params: change misc_reg count from 3 -> 6

From: Bill Huang New SoC's may have more then 3 MISC registers, so bump up the array size and use a #define to be more informative about the value. Signed-off-by: Bill Huang --- drivers/clk/tegra/clk.h |4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git

[PATCH v3 06/20] clk: tegra: pll-params: change misc_reg count from 3 - 6

From: Bill Huang bilhu...@nvidia.com New SoC's may have more then 3 MISC registers, so bump up the array size and use a #define to be more informative about the value. Signed-off-by: Bill Huang bilhu...@nvidia.com --- drivers/clk/tegra/clk.h |4 +++- 1 file changed, 3 insertions(+), 1