On Mon, Sep 10, 2012 at 06:29:21PM +0100, Nicolas Pitre wrote:
> On Mon, 10 Sep 2012, Catalin Marinas wrote:
>
> > On Fri, Sep 07, 2012 at 08:28:09PM +0100, Arnd Bergmann wrote:
> > > On Friday 07 September 2012, Catalin Marinas wrote:
> > > > +
> > > > +/*
> > > > + *
On Mon, Sep 10, 2012 at 06:29:21PM +0100, Nicolas Pitre wrote:
On Mon, 10 Sep 2012, Catalin Marinas wrote:
On Fri, Sep 07, 2012 at 08:28:09PM +0100, Arnd Bergmann wrote:
On Friday 07 September 2012, Catalin Marinas wrote:
+
+/*
+ * dmac_inv_range(start,end)
all of
On Thu, Sep 13, 2012 at 01:38:50PM +0100, Catalin Marinas wrote:
> On Wed, Sep 12, 2012 at 10:55:54PM +0100, Simon Baatz wrote:
> > On Wed, Sep 12, 2012 at 10:29:54AM +0100, Catalin Marinas wrote:
> ...
>
> > In case of direct I/O (and probably also in other cases like SG_IO)
> > the block layer
On Wed, Sep 12, 2012 at 10:55:54PM +0100, Simon Baatz wrote:
> On Wed, Sep 12, 2012 at 10:29:54AM +0100, Catalin Marinas wrote:
> > > > +void __flush_dcache_page(struct address_space *mapping, struct page
> > > > *page)
> > > > +{
> > > > + __flush_dcache_area(page_address(page), PAGE_SIZE);
On Wed, Sep 12, 2012 at 10:55:54PM +0100, Simon Baatz wrote:
On Wed, Sep 12, 2012 at 10:29:54AM +0100, Catalin Marinas wrote:
+void __flush_dcache_page(struct address_space *mapping, struct page
*page)
+{
+ __flush_dcache_area(page_address(page), PAGE_SIZE);
+}
+
On Thu, Sep 13, 2012 at 01:38:50PM +0100, Catalin Marinas wrote:
On Wed, Sep 12, 2012 at 10:55:54PM +0100, Simon Baatz wrote:
On Wed, Sep 12, 2012 at 10:29:54AM +0100, Catalin Marinas wrote:
...
In case of direct I/O (and probably also in other cases like SG_IO)
the block layer will see
Hi Catalin,
On Wed, Sep 12, 2012 at 10:29:54AM +0100, Catalin Marinas wrote:
>
> > > +void __flush_dcache_page(struct address_space *mapping, struct page
> > > *page)
> > > +{
> > > + __flush_dcache_area(page_address(page), PAGE_SIZE);
> > > +}
> > > +
> > > +void __sync_icache_dcache(pte_t
Hi Simon,
On Fri, Sep 07, 2012 at 08:35:42PM +0100, Simon Baatz wrote:
> On Fri, Sep 07, 2012 at 05:26:44PM +0100, Catalin Marinas wrote:
> > +#define ARCH_HAS_FLUSH_ANON_PAGE
> > +static inline void flush_anon_page(struct vm_area_struct *vma,
> > + struct page *page,
Hi Simon,
On Fri, Sep 07, 2012 at 08:35:42PM +0100, Simon Baatz wrote:
On Fri, Sep 07, 2012 at 05:26:44PM +0100, Catalin Marinas wrote:
+#define ARCH_HAS_FLUSH_ANON_PAGE
+static inline void flush_anon_page(struct vm_area_struct *vma,
+ struct page *page, unsigned long
Hi Catalin,
On Wed, Sep 12, 2012 at 10:29:54AM +0100, Catalin Marinas wrote:
+void __flush_dcache_page(struct address_space *mapping, struct page
*page)
+{
+ __flush_dcache_area(page_address(page), PAGE_SIZE);
+}
+
+void __sync_icache_dcache(pte_t pte)
+{
+
On Mon, 10 Sep 2012, Catalin Marinas wrote:
> On Fri, Sep 07, 2012 at 08:28:09PM +0100, Arnd Bergmann wrote:
> > On Friday 07 September 2012, Catalin Marinas wrote:
> > > +
> > > +/*
> > > + * dmac_inv_range(start,end)
> >
> > all of these appear to be unused now. Can you remove them?
>
>
On Fri, Sep 07, 2012 at 08:28:09PM +0100, Arnd Bergmann wrote:
> On Friday 07 September 2012, Catalin Marinas wrote:
> > +
> > +/*
> > + * dmac_inv_range(start,end)
>
> all of these appear to be unused now. Can you remove them?
They aren't currently used but I expect some partners to make use of
On Fri, Sep 07, 2012 at 08:28:09PM +0100, Arnd Bergmann wrote:
On Friday 07 September 2012, Catalin Marinas wrote:
+
+/*
+ * dmac_inv_range(start,end)
all of these appear to be unused now. Can you remove them?
They aren't currently used but I expect some partners to make use of
them on
On Mon, 10 Sep 2012, Catalin Marinas wrote:
On Fri, Sep 07, 2012 at 08:28:09PM +0100, Arnd Bergmann wrote:
On Friday 07 September 2012, Catalin Marinas wrote:
+
+/*
+ * dmac_inv_range(start,end)
all of these appear to be unused now. Can you remove them?
They aren't
Hi Catalin,
On Fri, Sep 07, 2012 at 05:26:44PM +0100, Catalin Marinas wrote:
> The patch adds functionality required for cache maintenance. The AArch64
> architecture mandates non-aliasing VIPT or PIPT D-cache and VIPT (may
> have aliases) or ASID-tagged VIVT I-cache. Cache maintenance operations
On Friday 07 September 2012, Catalin Marinas wrote:
> +
> +/*
> + * dmac_inv_range(start,end)
all of these appear to be unused now. Can you remove them?
> + * Invalidate the data cache within the specified region; we will be
> + * performing a DMA operation in this region and we want to
The patch adds functionality required for cache maintenance. The AArch64
architecture mandates non-aliasing VIPT or PIPT D-cache and VIPT (may
have aliases) or ASID-tagged VIVT I-cache. Cache maintenance operations
are automatically broadcast in hardware between CPUs.
Signed-off-by: Will Deacon
The patch adds functionality required for cache maintenance. The AArch64
architecture mandates non-aliasing VIPT or PIPT D-cache and VIPT (may
have aliases) or ASID-tagged VIVT I-cache. Cache maintenance operations
are automatically broadcast in hardware between CPUs.
Signed-off-by: Will Deacon
On Friday 07 September 2012, Catalin Marinas wrote:
+
+/*
+ * dmac_inv_range(start,end)
all of these appear to be unused now. Can you remove them?
+ * Invalidate the data cache within the specified region; we will be
+ * performing a DMA operation in this region and we want to purge
Hi Catalin,
On Fri, Sep 07, 2012 at 05:26:44PM +0100, Catalin Marinas wrote:
The patch adds functionality required for cache maintenance. The AArch64
architecture mandates non-aliasing VIPT or PIPT D-cache and VIPT (may
have aliases) or ASID-tagged VIVT I-cache. Cache maintenance operations
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