Re: [PATCH v3 1/2] dt-bindings: riscv: Update l2 cache DT documentation to add support for SiFive FU740

On Thu, 10 Dec 2020 15:58:02 +0530, Yash Shah wrote: > The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as > compared to 3 in FU540. Update the DT documentation accordingly with > "compatible" and "interrupt" property changes. > > Signed-off-by: Yash Shah > --- >

Re: [PATCH v3 1/2] dt-bindings: riscv: Update l2 cache DT documentation to add support for SiFive FU740

On Thu, 10 Dec 2020 02:28:02 PST (-0800), yash.s...@sifive.com wrote: The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as compared to 3 in FU540. Update the DT documentation accordingly with "compatible" and "interrupt" property changes. This generally looks good to me, but

[PATCH v3 1/2] dt-bindings: riscv: Update l2 cache DT documentation to add support for SiFive FU740

The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as compared to 3 in FU540. Update the DT documentation accordingly with "compatible" and "interrupt" property changes. Signed-off-by: Yash Shah --- .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 34 +++---