Hi Balbir,
On Tue, Nov 29, 2016 at 09:42:20PM +1100, Balbir Singh wrote:
>
>
> On 10/11/16 18:54, Gautham R. Shenoy wrote:
> > From: "Gautham R. Shenoy"
> >
> > Currently all the low-power idle states are expected to wake up
> > at reset vector 0x100. Which is why the
Hi Balbir,
On Tue, Nov 29, 2016 at 09:42:20PM +1100, Balbir Singh wrote:
>
>
> On 10/11/16 18:54, Gautham R. Shenoy wrote:
> > From: "Gautham R. Shenoy"
> >
> > Currently all the low-power idle states are expected to wake up
> > at reset vector 0x100. Which is why the macro
On 10/11/16 18:54, Gautham R. Shenoy wrote:
> From: "Gautham R. Shenoy"
>
> Currently all the low-power idle states are expected to wake up
> at reset vector 0x100. Which is why the macro IDLE_STATE_ENTER_SEQ
> that puts the CPU to an idle state and never returns.
>
>
On 10/11/16 18:54, Gautham R. Shenoy wrote:
> From: "Gautham R. Shenoy"
>
> Currently all the low-power idle states are expected to wake up
> at reset vector 0x100. Which is why the macro IDLE_STATE_ENTER_SEQ
> that puts the CPU to an idle state and never returns.
>
> On ISA_300, when the ESL
From: "Gautham R. Shenoy"
Currently all the low-power idle states are expected to wake up
at reset vector 0x100. Which is why the macro IDLE_STATE_ENTER_SEQ
that puts the CPU to an idle state and never returns.
On ISA_300, when the ESL and EC bits in the PSSCR are zero,
From: "Gautham R. Shenoy"
Currently all the low-power idle states are expected to wake up
at reset vector 0x100. Which is why the macro IDLE_STATE_ENTER_SEQ
that puts the CPU to an idle state and never returns.
On ISA_300, when the ESL and EC bits in the PSSCR are zero, the
CPU is expected to
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