Re: [PATCH v3 1/6] irqchip: sifive-plic: Pre-compute context hart base and enable base

On Mon, Dec 17, 2018 at 11:55 PM Christoph Hellwig wrote: > > On Fri, Nov 30, 2018 at 01:32:02PM +0530, Anup Patel wrote: > > This patch does following optimizations: > > 1. Pre-compute hart base for each context handler > > 2. Pre-compute enable base for each context handler > > 3. Have enable

Re: [PATCH v3 1/6] irqchip: sifive-plic: Pre-compute context hart base and enable base

On Fri, Nov 30, 2018 at 01:32:02PM +0530, Anup Patel wrote: > This patch does following optimizations: > 1. Pre-compute hart base for each context handler > 2. Pre-compute enable base for each context handler > 3. Have enable lock for each context handler instead > of global plic_toggle_lock All

[PATCH v3 1/6] irqchip: sifive-plic: Pre-compute context hart base and enable base

This patch does following optimizations: 1. Pre-compute hart base for each context handler 2. Pre-compute enable base for each context handler 3. Have enable lock for each context handler instead of global plic_toggle_lock Signed-off-by: Anup Patel --- drivers/irqchip/irq-sifive-plic.c | 47

[PATCH v3 1/6] irqchip: sifive-plic: Pre-compute context hart base and enable base

This patch does following optimizations: 1. Pre-compute hart base for each context handler 2. Pre-compute enable base for each context handler 3. Have enable lock for each context handler instead of global plic_toggle_lock Signed-off-by: Anup Patel --- drivers/irqchip/irq-sifive-plic.c | 47