Re: [PATCH v3 2/2] RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs

On Tue, May 7, 2019 at 7:15 PM Andrew F. Davis wrote: > > On 5/7/19 2:48 AM, Yash Shah wrote: > > On Mon, May 6, 2019 at 5:48 PM Andrew F. Davis wrote: > >> > >> On 5/6/19 6:48 AM, Yash Shah wrote: > >>> The driver currently supports only SiFive FU540-C000 platform. > >>> > >>> The initial

Re: [PATCH v3 2/2] RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs

On 5/7/19 2:48 AM, Yash Shah wrote: > On Mon, May 6, 2019 at 5:48 PM Andrew F. Davis wrote: >> >> On 5/6/19 6:48 AM, Yash Shah wrote: >>> The driver currently supports only SiFive FU540-C000 platform. >>> >>> The initial version of L2 cache controller driver includes: >>> - Initial configuration

Re: [PATCH v3 2/2] RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs

On Mon, May 6, 2019 at 5:48 PM Andrew F. Davis wrote: > > On 5/6/19 6:48 AM, Yash Shah wrote: > > The driver currently supports only SiFive FU540-C000 platform. > > > > The initial version of L2 cache controller driver includes: > > - Initial configuration reporting at boot up. > > - Support for

Re: [PATCH v3 2/2] RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs

On 5/6/19 6:48 AM, Yash Shah wrote: > The driver currently supports only SiFive FU540-C000 platform. > > The initial version of L2 cache controller driver includes: > - Initial configuration reporting at boot up. > - Support for ECC related functionality. > > Signed-off-by: Yash Shah > --- >

[PATCH v3 2/2] RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs

The driver currently supports only SiFive FU540-C000 platform. The initial version of L2 cache controller driver includes: - Initial configuration reporting at boot up. - Support for ECC related functionality. Signed-off-by: Yash Shah --- arch/riscv/include/asm/sifive_l2_cache.h | 16 +++