On Mon, Jun 6, 2016 at 10:56 AM, Marc Zyngier wrote:
> The ARM architected timer specification mandates that the interrupt
> associated with each timer is level triggered (which corresponds to
> the "counter >= comparator" condition).
>
> A number of DTs are being remarkably
On Mon, Jun 6, 2016 at 10:56 AM, Marc Zyngier wrote:
> The ARM architected timer specification mandates that the interrupt
> associated with each timer is level triggered (which corresponds to
> the "counter >= comparator" condition).
>
> A number of DTs are being remarkably creative, declaring
On Fri, 10 Jun 2016 10:32:24 -0700
David Daney wrote:
> On 06/10/2016 09:56 AM, Marc Zyngier wrote:
> > On 10/06/16 17:50, David Daney wrote:
> >> On 06/10/2016 12:23 AM, Marc Zyngier wrote:
> >>> On Thu, 09 Jun 2016 14:06:02 -0700
> >>> David Daney
On Fri, 10 Jun 2016 10:32:24 -0700
David Daney wrote:
> On 06/10/2016 09:56 AM, Marc Zyngier wrote:
> > On 10/06/16 17:50, David Daney wrote:
> >> On 06/10/2016 12:23 AM, Marc Zyngier wrote:
> >>> On Thu, 09 Jun 2016 14:06:02 -0700
> >>> David Daney wrote:
> >>>
> I spoke too soon...
>
On Mon, Jun 6, 2016 at 10:56 AM, Marc Zyngier wrote:
> The ARM architected timer specification mandates that the interrupt
> associated with each timer is level triggered (which corresponds to
> the "counter >= comparator" condition).
>
> A number of DTs are being remarkably
On Mon, Jun 6, 2016 at 10:56 AM, Marc Zyngier wrote:
> The ARM architected timer specification mandates that the interrupt
> associated with each timer is level triggered (which corresponds to
> the "counter >= comparator" condition).
>
> A number of DTs are being remarkably creative, declaring
On 06/10/2016 09:56 AM, Marc Zyngier wrote:
On 10/06/16 17:50, David Daney wrote:
On 06/10/2016 12:23 AM, Marc Zyngier wrote:
On Thu, 09 Jun 2016 14:06:02 -0700
David Daney wrote:
I spoke too soon...
On 06/09/2016 11:11 AM, David Daney wrote:
On 06/06/2016 10:56 AM,
On 06/10/2016 09:56 AM, Marc Zyngier wrote:
On 10/06/16 17:50, David Daney wrote:
On 06/10/2016 12:23 AM, Marc Zyngier wrote:
On Thu, 09 Jun 2016 14:06:02 -0700
David Daney wrote:
I spoke too soon...
On 06/09/2016 11:11 AM, David Daney wrote:
On 06/06/2016 10:56 AM, Marc Zyngier wrote:
On 10/06/16 17:50, David Daney wrote:
> On 06/10/2016 12:23 AM, Marc Zyngier wrote:
>> On Thu, 09 Jun 2016 14:06:02 -0700
>> David Daney wrote:
>>
>>> I spoke too soon...
>>>
>>> On 06/09/2016 11:11 AM, David Daney wrote:
On 06/06/2016 10:56 AM, Marc Zyngier wrote:
On 10/06/16 17:50, David Daney wrote:
> On 06/10/2016 12:23 AM, Marc Zyngier wrote:
>> On Thu, 09 Jun 2016 14:06:02 -0700
>> David Daney wrote:
>>
>>> I spoke too soon...
>>>
>>> On 06/09/2016 11:11 AM, David Daney wrote:
On 06/06/2016 10:56 AM, Marc Zyngier wrote:
> The ARM architected
On 06/10/2016 12:23 AM, Marc Zyngier wrote:
On Thu, 09 Jun 2016 14:06:02 -0700
David Daney wrote:
I spoke too soon...
On 06/09/2016 11:11 AM, David Daney wrote:
On 06/06/2016 10:56 AM, Marc Zyngier wrote:
The ARM architected timer specification mandates that the
On 06/10/2016 12:23 AM, Marc Zyngier wrote:
On Thu, 09 Jun 2016 14:06:02 -0700
David Daney wrote:
I spoke too soon...
On 06/09/2016 11:11 AM, David Daney wrote:
On 06/06/2016 10:56 AM, Marc Zyngier wrote:
The ARM architected timer specification mandates that the interrupt
associated with
On Thu, 09 Jun 2016 14:06:02 -0700
David Daney wrote:
> I spoke too soon...
>
> On 06/09/2016 11:11 AM, David Daney wrote:
> > On 06/06/2016 10:56 AM, Marc Zyngier wrote:
> >> The ARM architected timer specification mandates that the interrupt
> >> associated with each
On Thu, 09 Jun 2016 14:06:02 -0700
David Daney wrote:
> I spoke too soon...
>
> On 06/09/2016 11:11 AM, David Daney wrote:
> > On 06/06/2016 10:56 AM, Marc Zyngier wrote:
> >> The ARM architected timer specification mandates that the interrupt
> >> associated with each timer is level triggered
I spoke too soon...
On 06/09/2016 11:11 AM, David Daney wrote:
On 06/06/2016 10:56 AM, Marc Zyngier wrote:
The ARM architected timer specification mandates that the interrupt
associated with each timer is level triggered (which corresponds to
the "counter >= comparator" condition).
A number
I spoke too soon...
On 06/09/2016 11:11 AM, David Daney wrote:
On 06/06/2016 10:56 AM, Marc Zyngier wrote:
The ARM architected timer specification mandates that the interrupt
associated with each timer is level triggered (which corresponds to
the "counter >= comparator" condition).
A number
On 06/06/2016 10:56 AM, Marc Zyngier wrote:
The ARM architected timer specification mandates that the interrupt
associated with each timer is level triggered (which corresponds to
the "counter >= comparator" condition).
A number of DTs are being remarkably creative, declaring the interrupt
to
On 06/06/2016 10:56 AM, Marc Zyngier wrote:
The ARM architected timer specification mandates that the interrupt
associated with each timer is level triggered (which corresponds to
the "counter >= comparator" condition).
A number of DTs are being remarkably creative, declaring the interrupt
to
On 06/06/2016 12:56 PM, Marc Zyngier wrote:
> The ARM architected timer specification mandates that the interrupt
> associated with each timer is level triggered (which corresponds to
> the "counter >= comparator" condition).
>
> A number of DTs are being remarkably creative, declaring the
On 06/06/2016 12:56 PM, Marc Zyngier wrote:
> The ARM architected timer specification mandates that the interrupt
> associated with each timer is level triggered (which corresponds to
> the "counter >= comparator" condition).
>
> A number of DTs are being remarkably creative, declaring the
On 06/06/16 18:56, Marc Zyngier wrote:
> The ARM architected timer specification mandates that the interrupt
> associated with each timer is level triggered (which corresponds to
> the "counter >= comparator" condition).
>
> A number of DTs are being remarkably creative, declaring the interrupt
>
On 06/06/16 18:56, Marc Zyngier wrote:
> The ARM architected timer specification mandates that the interrupt
> associated with each timer is level triggered (which corresponds to
> the "counter >= comparator" condition).
>
> A number of DTs are being remarkably creative, declaring the interrupt
>
On 6.6.2016 19:56, Marc Zyngier wrote:
> The ARM architected timer specification mandates that the interrupt
> associated with each timer is level triggered (which corresponds to
> the "counter >= comparator" condition).
>
> A number of DTs are being remarkably creative, declaring the interrupt
>
On 6.6.2016 19:56, Marc Zyngier wrote:
> The ARM architected timer specification mandates that the interrupt
> associated with each timer is level triggered (which corresponds to
> the "counter >= comparator" condition).
>
> A number of DTs are being remarkably creative, declaring the interrupt
>
On 06/06/2016 07:56 PM, Marc Zyngier wrote:
> The ARM architected timer specification mandates that the interrupt
> associated with each timer is level triggered (which corresponds to
> the "counter >= comparator" condition).
>
> A number of DTs are being remarkably creative, declaring the
On 06/06/2016 07:56 PM, Marc Zyngier wrote:
> The ARM architected timer specification mandates that the interrupt
> associated with each timer is level triggered (which corresponds to
> the "counter >= comparator" condition).
>
> A number of DTs are being remarkably creative, declaring the
The ARM architected timer specification mandates that the interrupt
associated with each timer is level triggered (which corresponds to
the "counter >= comparator" condition).
A number of DTs are being remarkably creative, declaring the interrupt
to be edge triggered. A quick look at the TRM for
The ARM architected timer specification mandates that the interrupt
associated with each timer is level triggered (which corresponds to
the "counter >= comparator" condition).
A number of DTs are being remarkably creative, declaring the interrupt
to be edge triggered. A quick look at the TRM for
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