Re: [PATCH v3 2/2] phy: rockchip-inno-usb2: correct 480MHz output clock stable time

Hi Doug, 在 2016年11月15日 02:17, Doug Anderson 写道: William, On Mon, Nov 14, 2016 at 1:27 AM, William Wu wrote: We found that the system crashed due to 480MHz output clock of USB2 PHY was unstable after clock had been enabled by gpu module. Theoretically, 1 millisecond is a

Re: [PATCH v3 2/2] phy: rockchip-inno-usb2: correct 480MHz output clock stable time

Hi Doug, 在 2016年11月15日 02:17, Doug Anderson 写道: William, On Mon, Nov 14, 2016 at 1:27 AM, William Wu wrote: We found that the system crashed due to 480MHz output clock of USB2 PHY was unstable after clock had been enabled by gpu module. Theoretically, 1 millisecond is a critical value for

Re: [PATCH v3 2/2] phy: rockchip-inno-usb2: correct 480MHz output clock stable time

William, On Mon, Nov 14, 2016 at 1:27 AM, William Wu wrote: > We found that the system crashed due to 480MHz output clock of > USB2 PHY was unstable after clock had been enabled by gpu module. > > Theoretically, 1 millisecond is a critical value for 480MHz > output clock

Re: [PATCH v3 2/2] phy: rockchip-inno-usb2: correct 480MHz output clock stable time

William, On Mon, Nov 14, 2016 at 1:27 AM, William Wu wrote: > We found that the system crashed due to 480MHz output clock of > USB2 PHY was unstable after clock had been enabled by gpu module. > > Theoretically, 1 millisecond is a critical value for 480MHz > output clock stable time, so we try

[PATCH v3 2/2] phy: rockchip-inno-usb2: correct 480MHz output clock stable time

We found that the system crashed due to 480MHz output clock of USB2 PHY was unstable after clock had been enabled by gpu module. Theoretically, 1 millisecond is a critical value for 480MHz output clock stable time, so we try to change the delay time to 1.2 millisecond to avoid this issue. And

[PATCH v3 2/2] phy: rockchip-inno-usb2: correct 480MHz output clock stable time

We found that the system crashed due to 480MHz output clock of USB2 PHY was unstable after clock had been enabled by gpu module. Theoretically, 1 millisecond is a critical value for 480MHz output clock stable time, so we try to change the delay time to 1.2 millisecond to avoid this issue. And